Power saving processing system

• US 5,560,020 A
• Filed: 09/20/1991
• Issued: 09/24/1996
• Est. Priority Date: 09/21/1990
• Status: Expired due to Term

• Current Assignee: Hitachi Consumer Electronics Company Limited (Hitachi, Ltd.)
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakatani, Kohichi, Hayashi, Akio, Kohiyama, Tomohisa
• Primary Examiner(s): Davis, George B.
• Application Number:
  US07/763,152
• Time in Patent Office: 1,831 Days
• Field of Search: 395/750, 395/375, 395/550, 364/200, 364/900, 364/707, 364/DIG. 1, 364/DIG 2, 365/227
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data processing system which has a processor which issues a key sensing signal when waiting for the input of data; a discriminator connected to the processor for judging whether a key sensing signal is received from the processor and for generating a first signal; a controller for generating a second signal in response to the first signal received from the discriminator; and a switch for selecting one of a plurality of clock signals of different frequency to be sent to the processor in response to the second signal received from the controller. Generation of the second signal can be delayed by a first predetermined time, and a second predetermined time during which the key sensing signal is not received can be measured, whereby it is unnecessary to modify an application program to control the supply of power to the processor and only modification of a key sensing routine (BIOS) enables realization of positive power saving.

Claims

1. A data processing system comprising:

a processor which calls a key sense routine to issue a flag set instruction pulse signal on a system bus when waiting for input of data;

discrimination means for receiving said flag set instruction pulse signal from said processor and generating a first signal when said flag set instruction pulse signal is received,

wherein said discrimination means includes time measuring means for measuring a first predetermined time during which said flag set instruction pulse signal is not received, and

wherein said time measuring means includes first free running counter means which is reset by a pulse in said flag set instruction pulse signal, first register means having stored therein a value corresponding to said first predetermined time, first comparator means for comparing an output of said first free running counter means with an output of said first register means, and first flag means for receiving said flag set instruction pulse signal as a set input and receiving an output of said first comparator means as a reset input;

control means for generating a second signal in response to receipt of said first signal from said discrimination means; and

switch means for selecting one of at least two clock signals of different frequencies to be sent to said processor in response to presence or absence of receipt of said second signal from said control means.

2. A data processing system comprising:

a processor which calls a key sensing routine to issue a flag set instruction pulse signal on a system bus when waiting for input of data;

discrimination means for receiving said flag set instruction pulse signal from said processor and generating a first signal when said flag set instruction pulse signal is issued;

control means for generating a second signal in response to receipt of said first signal from said discrimination means,

wherein said control means includes second free running counter means which is reset in response to said first signal received from said discrimination means, second register means having stored therein a value corresponding to said first predetermined time, and second comparator means for comparing an output of said second free running counter means with an output of said second register means; and

switch means for selecting one of at least two clock signals of different frequency to be sent to said processor in response to presence or absence of receipt of said second signal from said control means.

3. A data processing system as set forth in claim 2, wherein said control means further includes flag means which is reset by said first signal received from said discrimination means and set by an output of said second comparator means.