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Power saving processing system

  • US 5,560,020 A
  • Filed: 09/20/1991
  • Issued: 09/24/1996
  • Est. Priority Date: 09/21/1990
  • Status: Expired due to Term
First Claim
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1. A data processing system comprising:

  • a processor which calls a key sense routine to issue a flag set instruction pulse signal on a system bus when waiting for input of data;

    discrimination means for receiving said flag set instruction pulse signal from said processor and generating a first signal when said flag set instruction pulse signal is received,wherein said discrimination means includes time measuring means for measuring a first predetermined time during which said flag set instruction pulse signal is not received, andwherein said time measuring means includes first free running counter means which is reset by a pulse in said flag set instruction pulse signal, first register means having stored therein a value corresponding to said first predetermined time, first comparator means for comparing an output of said first free running counter means with an output of said first register means, and first flag means for receiving said flag set instruction pulse signal as a set input and receiving an output of said first comparator means as a reset input;

    control means for generating a second signal in response to receipt of said first signal from said discrimination means; and

    switch means for selecting one of at least two clock signals of different frequencies to be sent to said processor in response to presence or absence of receipt of said second signal from said control means.

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