Computer power management system

• US 5,560,024 A
• Filed: 02/01/1995
• Issued: 09/24/1996
• Est. Priority Date: 06/30/1989
• Status: Expired due to Fees

• Current Assignee: Fujitsu Personal Systems, Inc. (Fujitsu Limited)
• Original Assignee: Fujitsu Personal Systems, Inc. (Fujitsu Limited)
• Inventors: Stone, Roderick W., Hooks, Douglas A., Cullimore, Ian H. S., Schlichting, Grayson C., Harper, Leroy D., Bradshaw, Gavin A., Fairbanks, John P., Banerjee, Biswa R.
• Primary Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US08/384,284
• Time in Patent Office: 601 Days
• Field of Search: 395/750, 395/550, 364/707
• US Class Current: 713/322
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A low power management system including both hardware and software is provided for a battery powered portable computer. The low power management system powers down various sections of the computer when they are not used. The low power management system is controlled by a control program in the microprocessor of the computer. The low power management system includes the capability to turn off clock signals to various sections of the computer based upon demand. Also included is the capability to turn on clock signals based upon demand. The low power management system also includes the capability to turn on the computer upon a press of a key on the computer keyboard. The low power management system monitors software application programs for keyboard activity so as to turn off the microprocessor in the computer in response to a loop looking for a keypress and certain other loops which can be monitored without use of the microprocessor.

Claims

1. A method for reducing power consumed by a computer having a processor for executing at least one application program and having a manual input device for inputting data to the processor, the application program generating interrupts to call for receiving the data input from the manual input device, the method comprising the steps of:

during execution of the application program, counting a first number of the interrupts generated by the application program during a first time interval of predetermined duration;

counting a second number of the interrupts generated by the application program during a second time interval of equal duration and subsequent to the first;

determining a difference between the first number and the second number; and

reducing power consumed by the processor if the difference is within a predetermined range.

2. The method of claim 1, wherein the step of reducing power is undertaken only if the first number is at least four interrupts per a time interval of 1/18 second duration.

3. The method of claim 1, wherein the step of reducing power comprises the step of turning off a clock signal, said clock signal being provided for controlling the processor.

4. The method of claim 3, further comprising, after the step of reducing power, the step of externally turning on said clock signal.

5. The method of claim 3, further comprising, after the step of reducing power, the step of turning on said clock signal in response to detection of a data input from the manual input device.

6. The method of claim 1, wherein said interrupts are calls for a status of the manual input device.

7. The method of claim 1, wherein the manual input device is a keyboard.

8. The method of claim 1, wherein the step of reducing power includes the step of operating the processor at a reduced clock frequency.

9. A method for reducing power consumed by a computer having a processor for executing at least one application program and having a manual input device for inputting data to the processor, the application program generating interrupts for receiving the data from the manual input device, comprising the steps of:

during execution of the application program, counting a first number of the interrupts generated by the application program during a first time interval of predetermined duration;

counting a second number of the interrupts generated by the application program during a second time interval of equal duration and subsequent to the first;

counting a third number of the interrupts generated by the application program during a third time interval of equal duration and subsequent to the second; and

reducing power consumed by the processor if the third number is within a predetermined value of both the first and second numbers.

10. The method of claim 9, wherein the step of reducing power includes the step of operating the processor at a reduced clock frequency.

11. An apparatus for reducing power consumed by a computer having a processor for executing at least one application program and having a manual input device for inputting data to the processor, the application program generating interrupts to call for receiving the data from the manual input device, comprising:

means for counting a first number of the interrupts generated by the application program during a first time interval of predetermined duration during execution of the application program;

means for counting a second number of the interrupts generated by the application program during a second time interval of equal duration and subsequent to the first;

means for determining a difference between the first and second numbers, the means for determining being operatively connected to each of the means for counting; and

means for reducing power consumed by the processor if the difference is within a predetermined range, the means for reducing power being operatively connected to the means for determining a difference.

12. The apparatus of claim 11, further comprising a timing signal generator for generating clock signals for controlling the processor and being operatively connected to the processor;

wherein the means for reducing power comprises means for turning off the timing signal generator.

13. The apparatus of claim 11, wherein the means for reducing power includes means for operating the processor at a reduced clock frequency.