Scalable parallel processing systems wherein each hypernode has plural processing modules interconnected by crossbar and each processing module has SCI circuitry for forming multi-dimensional network with other hypernodes

• US 5,560,027 A
• Filed: 12/15/1993
• Issued: 09/24/1996
• Est. Priority Date: 12/15/1993
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Convex Computer Corp. (HP Inc.)
• Inventors: Brewer, Tony M., Chastain, David M., Watson, Thomas L.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): DINH, DUNG C
• Application Number:
  US08/167,663
• Time in Patent Office: 1,014 Days
• Field of Search: 395/800, 395/200.08, 395/311, 395/312
• US Class Current: 712/12
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus

Abstract

A processing system 100 is provided which includes first and second hypernodes 101, each of the hypernodes 101 having at least first and second coherent interfaces 106. At least first and second interconnect network 107 are provided, the first network 107 coupling the first interfaces 106 of the first and second hypernodes 101 and the second interconnect network 107 coupling the second interfaces 106 of the first and second hypernodes 101.

Claims

1. A processing system comprising:

first processing circuitry including a processor and a partially global memory coupled by associated control circuitry to a first crossbar and a first coherent interconnect network;

second processing circuitry including a processor and a partially global memory coupled by associated control circuitry to said first crossbar and a second coherent interconnect network;

third processing circuitry including a processor and a partially global memory coupled by associated control circuitry to a second crossbar and said first coherent interconnect network; and

fourth processing circuitry including a processor and a partially global memory coupled by associated control circuitry to said second crossbar and said second coherent interconnect network.

2. The system of claim 1 wherein said coherent interconnect network are constructed in accordance with IEEE standard 1596-1992.

3. The system of claim 1 wherein said interconnect network each include a pair of unidirectional links.

4. The system of claim 1 wherein said first and second processing circuitry and said first crossbar are coupled in a symmetric multiprocessor arrangement.

5. The system of claim 1 wherein said third and fourth processing circuitry and said second crossbar are coupled in a symmetric multiprocessor arrangement.

6. A processing system comprising:

at least first and second hypernodes, each of said hypernodes comprising;

at least first and second coherent interfaces;

first processing circuitry comprising;

at least one first central processing unit;

first memory circuitry, wherein a portion of said first memory is global;

first control circuitry coupled to said first central processing unit, said first memory circuitry, and said first coherent interface;

second processing circuitry comprising;

at least one second central processing unit;

second memory circuitry, wherein a portion of said second memory is global;

second control circuitry coupled to said second central processing unit, said second memory circuitry, and said second coherent interface;

interconnection circuitry coupled to said first and second control circuitries, wherein the interconnection circuitry comprises a crossbar;

at least first and second interleaved interconnect networks, said first interconnect network coupling said first coherent interfaces of said first and second hypernodes and said second interconnect network coupling said second coherent interfaces of said first and second hypernodes.

7. The processing system of claim 6, wherein said first and second coherent interfaces are constructed in accordance with IEEE standard 1596-1992.

8. The processing system of claim 6, wherein each of said hypernodes is arranged as a symmetric multiprocessor.

9. The processing system of claim 6, wherein a selected one of said first and second control circuitry comprises:

an agent coupled to said at least one central processing unit with said interconnection circuitry; and

a controller coupled to said agent, said memory, said interconnection circuitry, and a corresponding said coherent interface.

10. The processing system of claim 9, wherein said memory of said selected one of said first and second processing circuitry is partitioned by physical address into main memory and cache memory.

11. The processing circuitry of claim 10, wherein said cache memory comprises network cache memory.

12. The processing system of claim 11, wherein each of said hypernodes operates on data organized as cache lines each of a first number of bytes and each of said interconnect networks transfers data organized as cache lines of a second number of bytes, said network cache bridging one of said hypernodes and one of said networks when said first number of bytes and said second number of bytes are unequal.

13. The processing system of claim 6, wherein each of said interconnect networks comprises a pair of unidirectional interconnection links.

14. The processing system of claim 6, wherein at least one of said central processing units comprises a reduced instruction set architecture.

15. The processing system of claim 6, further comprising an input/output interface coupled to said crossbar.

16. The processing system of claim 6, wherein said first and second hypernodes and said first and second interleaved interconnect networks are arranged in a multi-dimensional space.