High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

• US 5,560,032 A
• Filed: 03/01/1995
• Issued: 09/24/1996
• Est. Priority Date: 07/08/1991
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Wang, Johannes, Wang, Sze-Shun, Nguyen, Le Trong, Miyayama, Yoshiyuki, Trang, Quang H., Lau, Te-Li, Garg, Sanjiv, Lentz, Derek J., Hagiwara, Yasuaki
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US08/397,016
• Time in Patent Office: 573 Days
• Field of Search: 395/800, 395/375, 395/475
• US Class Current: 712/23
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/323 for indirect branch instructions
• CPC Class Codes: G06F 9/327 for interrupts
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 : Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 : Register renaming
• CPC Class Codes: G06F 9/3853 : of compound instructions
• CPC Class Codes: G06F 9/3854 : Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3865 : using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A high-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution for enhanced resource utilization and performance throughput. The computer system architecture includes an instruction fetch unit for fetching program instruction sets. Each instruction set includes a plurality of fixed length instructions with a prescribed program order (in-order). The architecture also includes an instruction execution unit for dynamically examining the instruction sets and scheduling instructions for execution, including out-of-order execution, among a plurality of functional units. The data results of the executed instructions are concurrently distributed to a temporary buffer and a register file array and managed by associated control logic, including a register renaming unit, a dependency checker unit, done control unit, and retirement control unit. The architecture also optimizes the scheduling of data paths in accordance with the type of computational function, including integer, floating point, and boolean.

Claims

1. A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising:

first means for storing a source of operands corresponding to a plurality of instruction operations;

second means for concurrently transferring said operands from said first means to a plurality of functional units;

third means for performing said instruction operations to generate results using said plurality of functional units; and

fourth means for concurrently distributing said results,

wherein said first and fourth means including temporary buffer means selectively coupled with register file means, said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and

said register file means directly receives a result of an instruction operation from said fourth means, thereby bypassing said temporary buffer means, if said instruction operation is performed in said prescribed program order.

2. A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising:

first means for storing a source of operands corresponding to a plurality of instruction operations;

second means for concurrently transferring said operands from said first means to a plurality of functional units;

third means for performing said instruction operations to generate results using said plurality of functional units; and

fourth means for concurrently distributing said results,

wherein said first and fourth means including temporary buffer means selectively coupled with register file means, said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order,

said first means comprises a floating point register file and an integer register file, and said functional units comprise a floating point functional unit and an integer functional unit, and

said fourth means distributes floating point results to said integer file and distributes integer results to said floating point register file.

3. The superscalar processing system according to claim 2, further comprising a load/store unit, wherein said set of parallel buses further distributes said floating point results and said integer results to said load/store unit, and wherein said load/store unit stores said further distributed results to a memory unit.

4. The superscalar processing system according to claim 3, wherein said load/store unit loads data into at least one of said floating point register file and said integer register file.

5. The superscalar processing system according to claim 3, wherein said load/store unit loads data into at least one of said floating point functional units and said integer functional units.

6. A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising:

first means for storing a source of operands corresponding to a plurality of instruction operations;

second means for concurrently transferring said operands from said first means to a plurality of functional units;

third means for performing said instruction operations to generate results using said plurality of functional units; and

fourth means for concurrently distributing said results,

said first and fourth means including temporary buffer means selectively coupled with register file means,

wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order,

said first means comprises a floating point register file, an integer register file, and a boolean register file, and said functional units comprise a floating point functional unit and a integer functional unit, and

said fourth means distributes floating point results to one of said integer file and said boolean register file, and distributes integer results to one of said floating point register file and said boolean register file.

7. The superscalar processing system according to claim 6, further comprising a load/store unit, wherein said fourth means further distributes said floating point results and said integer results to said load/store unit, and wherein said load/store unit stores said further transferred results to a memory unit.

8. The superscalar processing system according to claim 7, wherein said load/store unit loads data into one of said floating point register, said integer register file and said boolean register file.

9. The superscalar processing system according to claim 7, wherein said load/store unit loads data into one of said floating point functional units and said integer functional units.

10. A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising:

first means for storing a source of operands corresponding to a plurality of instruction operations;

second means for concurrently transferring said operands from said first means to a plurality of functional units;

third means for performing said instruction operations to generate results using said plurality of functional units; and

fourth means for concurrently distributing said results,

wherein said first and fourth means including temporary buffer means selectively coupled with register file means, said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and

said second means transfers at least one operand from a floating point register file to an integer functional unit.

11. A superscalar processing system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, said superscalar processing system comprising:

first means for storing a source of operands corresponding to a plurality of instruction operations;

second means for concurrently transferring said operands from said first means to a plurality of functional units;

third means for performing said instruction operations to generate results using said plurality of functional units; and

fourth means for concurrently distributing said results,

said first and fourth means including temporary buffer means selectively coupled with register file means,

wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order,

said first means comprises a boolean register file and at least one of a floating point register file and an integer register file, and said functional units comprise a floating point functional unit and an integer functional unit, and

said fourth means comprise a set of parallel buses that distributes floating point results to at least one of said integer file and said boolean register file, and distributes integer results to at least one of said floating point register file and said boolean register file.

12. The superscalar processing system according to claim 11, further comprising a load/store unit, wherein said fourth means further distributes said floating point results and said integer results to said load/store unit, and wherein said load/store unit further distributes said results to a memory unit.

13. The superscalar processing system according to claim 12, wherein said load/store unit loads data into at least one of said floating point register file, said integer register file and said boolean register file.

14. The superscalar processing system according to claim 12, wherein said load/store unit loads data into at least one of said floating point functional units and said integer functional units.

15. A method for processing data in a superscalar system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, wherein said superscalar system also has a temporary buffer and register file for storing results, the method comprising the steps of:

storing a source of operands corresponding to a plurality of instruction operations;

concurrently transferring said operands to a plurality of functional units;

performing said instruction operations to generate results using said plurality of functional units;

concurrently distributing said results;

distributing floating point results to an integer file; and

distributing integer results to a floating point register file using a set of parallel buses,

wherein said storing step is performed by storing said results in the temporary buffer, rather than the register file means, if said results are distributed out-of-order with respect to said prescribed program order.

16. The method according to claim 15, further comprising the step of distributing said floating point results and said integer results to a load/store unit.

17. The method according to claim 16, further comprising the step of storing said further distributed results in a memory unit.

18. A method for processing data in a superscalar system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, wherein said superscalar system also has a temporary buffer and register file for storing results, the method comprising the steps of:

storing a source of operands corresponding to a plurality of instruction operations;

concurrently transferring said operands to a plurality of functional units;

performing said instruction operations to generate results using said plurality of functional units;

concurrently distributing said results;

transferring floating point results to one of a integer file and a boolean register file; and

transferring integer results to one of said floating point register file and said boolean register file using a set of parallel buses,

wherein said storing step is performed by storing said results in the temporary buffer, rather than the register file means, if said results are distributed out-of-order with respect to said prescribed program order.

19. The method according to claim 18, further comprising the step of distributing said floating point results and said integer results to a load/store unit.

20. The method according to claim 19, further comprising the step of storing said further distributed results in a memory unit.

21. A computer system, comprising:

main memory bus;

input/output bus; and

a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having;

a first stage for decoding and issuing instructions in a prescribed program order;

a second stage for executing instructions out-of-order with respect to said prescribed program order;

first means for storing a source of operands corresponding to a plurality of instruction operations;

second means for concurrently transferring said operands from said first means to a plurality of functional units;

third means for performing said instruction operations to generate results using said plurality of functional units; and

fourth means for concurrently distributing said results,

wherein said first and fourth means including temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order,

said first means comprises a boolean register file and at least one of a floating point register file and an integer register file, and wherein said functional units comprise a floating point functional unit and an integer functional unit, and

said fourth means comprise a set of parallel buses that distributes floating point results to at least one of said integer file and said boolean register file, and distributes integer results to at least one of said floating point register file and said boolean register file.

22. The computer system according to claim 21, further comprising a load/store unit, wherein said fourth means further distributes said floating point results and said integer results to said load/store unit, and wherein said load/store unit further distributes said results to a memory unit.

23. The computer system according to claim 22, wherein said load/store unit loads data into at least one of said floating point register file, said integer register file and said boolean register file.

24. The computer system according to claim 22, wherein said load/store unit loads data into at least one of said floating point functional units and said integer functional units.

25. A computer system, comprising:

main memory bus;

input/output bus; and

a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having;

a first stage for decoding and issuing instructions in a prescribed program order;

a second stage for executing instructions out-of-order with respect to said prescribed program order;

first means for storing a source of operands corresponding to a plurality of instruction operations;

second means for concurrently transferring said operands from said first means to a plurality of functional units;

third means for performing said instruction operations to generate results using said plurality of functional units; and

fourth means for concurrently distributing said results,

wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and

said register file means directly receives a result of an instruction operation from said fourth means, thereby bypassing said temporary buffer means, if said instruction operation is performed in said prescribed program order.

26. A computer system, comprising:

main memory bus;

input/output bus; and

a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having;

a first stage for decoding and issuing instructions in a prescribed program order;

a second stage for executing instructions out-of-order with respect to said prescribed program order;

first means for storing a source of operands corresponding to a plurality of instruction operations;

second means for concurrently transferring said operands from said first means to a plurality of functional units;

third means for performing said instruction operations to generate results using said plurality of functional units; and

fourth means for concurrently distributing said results,

wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order,

said first means comprises a floating point register file and an integer register file, and said functional units comprise a floating point functional unit and an integer functional unit, and

said fourth means distributes floating point results to said integer file and distributes integer results to said floating point register file.

27. A computer system, comprising:

main memory bus;

input/output bus; and

a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having;

a first stage for decoding and issuing instructions in a prescribed program order;

a second stage for executing instructions out-of-order with respect to said prescribed program order;

first means for storing a source of operands corresponding to a plurality of instruction operations;

second means for concurrently transferring said operands from said first means to a plurality of functional units;

third means for performing said instruction operations to generate results using said plurality of functional units; and

fourth means for concurrently distributing said results,

wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order,

said first means comprises a floating point register file, an integer register file, and a boolean register file, and said functional units comprise a floating point functional unit and an integer functional unit, and

said fourth means distributes floating point results to one of said integer file and said boolean register file, and distributes integer results to one of said floating point register file and said boolean register file.

28. A computer system, comprising:

main memory bus;

input/output bus; and

a superscalar processor, operably connected to said main memory and said input/output bus, said superscalar processing system having;

a first stage for decoding and issuing instructions in a prescribed program order;

a second stage for executing instructions out-of-order with respect to said prescribed program order;

first means for storing a source of operands corresponding to a plurality of instruction operations;

second means for concurrently transferring said operands from said first means to a plurality of functional units;

third means for performing said instruction operations to generate results using said plurality of functional units; and

fourth means for concurrently distributing said results,

wherein said first and fourth means include temporary buffer means selectively coupled with register file means, wherein said results are stored in said temporary buffer means rather than said register file means, if said results are distributed out-of-order with respect to said prescribed program order, and

said second means transfers at least one operand from a floating point register file to an integer functional unit.

29. A method for processing data in a superscalar system having a plurality of stages, including a first stage for decoding and issuing instructions in a prescribed program order and a second stage for executing instructions out-of-order with respect to said prescribed program order, wherein said superscalar system also has a temporary buffer and register file for storing results, the method comprising the steps of:

storing a source of operands corresponding to a plurality of instruction operations;

concurrently transferring said operands to a plurality of functional units;

performing said instruction operations to generate results using said plurality of functional units;

concurrently distributing said results; and

transferring at least one operand from a floating point register file to an integer functional unit,

wherein said storing step is performed by storing said results in the temporary buffer, rather than the register file means, if said results are distributed out-of-order with respect to said prescribed program order.