System for providing automatic power control for highly available n+k processors

• US 5,560,033 A
• Filed: 08/29/1994
• Issued: 09/24/1996
• Est. Priority Date: 08/29/1994
• Status: Expired due to Fees

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Kimber, Douglas A., Doherty, Brian P., Larson, Mikiel L., Pokropinski, John H.
• Primary Examiner(s): Geckil, Mehmet B.
• Application Number:
  US08/297,458
• Time in Patent Office: 757 Days
• Field of Search: 395/0, 395/575, 395/181, 395/182.02, 395/182.06, 395/182, 395/21.22, 395/800, 395/750, 395/185.09, 395/182.20, 395/200.11, 371/11.1, 371/14, 371/16.3
• US Class Current: 713/340
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/2023 Failover techniques
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 11/2736 using a dedicated service processor for test

Abstract

A highly available processor complex that can use industry standard hardware and software through use of an N+K sparing arrangement with a separate monitor ("watchdog") processor. The watchdog processor monitors periodic "heartbeat" messages from the monitored elements and can change activity and status of such monitored elements through control messages. Further, the watchdog processor is operatively connected to a power control circuit that controls the power to the monitored elements. Thus, the watchdog processor can guarantee that a faulty element can be rendered non-functional and can also totally restart an element through power cycling it.

Claims

1. An N+K sparing processing arrangement comprising:

a watchdog processor;

a plurality of processors connected to said watchdog processor for message communication, each of said plurality of processors sending periodic messages to said watchdog processor, said plurality of processors being configured into processing groups by said watchdog processor, each of said processing groups including one or more active processors and one or more spare processors, each processor in each group performing a similar task, and each group performing different tasks for the other groups; and

a plurality of power control circuits connected to each of said plurality of processors and each of said plurality of power control circuits communicating with said watchdog processor;

said watchdog processor reconfiguring said processing groups and taking corrective action in response to receipt or non-receipt of said periodic messages from said plurality of processors, said corrective action including causing said power control circuits to remove power from one or more of said plurality of processors.

2. An N+K sparing arrangement according to claim 1 further including a human-machine interface for causing said watchdog processor to change the configuration of said processing groups.