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Integrated circuit structure including CMOS devices protected by patterned nitride passivation and method for the fabrication thereof

  • US 5,561,319 A
  • Filed: 08/30/1994
  • Issued: 10/01/1996
  • Est. Priority Date: 05/14/1993
  • Status: Expired due to Term
First Claim
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1. An integrated circuit structure comprising:

  • (a) one or more MOS devices formed in said integrated circuit structure, each of said MOS devices comprising a thin gate oxide layer therein; and

    (b) a patterned silicon nitride passivation layer overlying an uppermost metallization layer of said integrated circuit structure, wherein said pattern of said patterned nitride passivation layer is formed such that openings in said patterned nitride passivation layer overlay said thin gate oxide layer of one or more of said MOS devices.

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