Integrated circuit structure including CMOS devices protected by patterned nitride passivation and method for the fabrication thereof
First Claim
Patent Images
1. An integrated circuit structure comprising:
- (a) one or more MOS devices formed in said integrated circuit structure, each of said MOS devices comprising a thin gate oxide layer therein; and
(b) a patterned silicon nitride passivation layer overlying an uppermost metallization layer of said integrated circuit structure, wherein said pattern of said patterned nitride passivation layer is formed such that openings in said patterned nitride passivation layer overlay said thin gate oxide layer of one or more of said MOS devices.
2 Assignments
0 Petitions
Accused Products
Abstract
A CMOS integrated circuit structure is disclosed having a patterned nitride passivation layer, wherein the nitride is patterned such that it does not overlie the thin gate oxide portions of one or more of the MOS devices. When protection against the effects of external radiation is desired, the thin gate oxide areas of the PMOS devices are left uncovered by the patterned nitride passivation layer. When protection is desired against the effects of internally generated "hot electrons", the thin gate oxide areas of the NMOS devices are left uncovered by the patterned nitride passivation layer.
-
Citations
25 Claims
-
1. An integrated circuit structure comprising:
-
(a) one or more MOS devices formed in said integrated circuit structure, each of said MOS devices comprising a thin gate oxide layer therein; and (b) a patterned silicon nitride passivation layer overlying an uppermost metallization layer of said integrated circuit structure, wherein said pattern of said patterned nitride passivation layer is formed such that openings in said patterned nitride passivation layer overlay said thin gate oxide layer of one or more of said MOS devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. An integrated circuit structure having protection therein from external radiation comprising:
-
(a) one or more PMOS devices and one or more NMOS devices formed in said integrated circuit structure, each of said PMOS and NMOS devices comprising a thin gate oxide layer therein; and (b) a patterned silicon nitride passivation layer overlying an uppermost metallization layer of said integrated circuit structure, wherein said pattern of said patterned nitride passivation layer is formed such that openings in said patterned nitride passivation layer overlay said thin gate oxide layer of one or more of said PMOS devices.
-
-
17. An integrated circuit structure having protection therein from hot electrons generated therein comprising:
-
(a) one or more PMOS devices and one or more NMOS devices formed in said integrated circuit structure, each of said PMOS and NMOS devices comprising a thin gate oxide layer therein; and (b) a patterned silicon nitride passivation layer overlying an uppermost metallization layer of said integrated circuit structure, wherein said pattern of said patterned nitride passivation layer is formed such that openings in said patterned nitride passivation layer overlay said thin gate oxide layer of one or more of said NMOS devices.
-
-
18. A method of fabricating an integrated circuit structure comprising:
-
(a) providing one or more MOS devices in said integrated circuit structure, each of said MOS devices comprising a thin gate oxide layer therein; and (b) forming a patterned silicon nitride passivation layer over an uppermost metallization layer of said integrated circuit structure, said patterned nitride passivation layer having openings in said pattern positioned such that said openings in said patterned nitride passivation layer overlay said thin gate oxide layer of one or more of said MOS devices. - View Dependent Claims (19, 20, 21, 22)
-
-
23. A method of fabricating an integrated circuit structure having protection against externally generated radiation comprising:
-
(a) providing one or more PMOS devices and one or more NMOS devices in said integrated circuit structure, each of said PMOS and NMOS devices comprising a thin gate oxide layer therein; and (b) forming a patterned silicon nitride passivation layer over an uppermost metallization layer of said integrated circuit structure, said patterned nitride passivation layer having openings in said pattern positioned such that said openings in said patterned nitride passivation layer overlay said thin gate oxide layer of one or more of said PMOS devices.
-
-
24. A method of fabricating an integrated circuit structure having protection against internally generated hot electrons comprising:
-
(a) providing one or more PMOS devices and one or more NMOS devices in said integrated circuit structure, each of said PMOS and NMOS devices comprising a thin gate oxide layer therein; and (b) forming a patterned silicon nitride passivation layer over an uppermost metallization layer of said integrated circuit structure, said patterned nitride passivation layer having openings in said pattern positioned such that said openings in said patterned nitride passivation layer overlay said thin gate oxide layer of one or more of said NMOS devices.
-
-
25. An integrated circuit structure comprising:
-
(a) one or more MOS devices formed in said integrated circuit structure, each of said MOS devices comprising a thin gate oxide layer therein defining the area in said integrated circuit structure in which said MOS device is formed; and (b) a patterned silicon nitride passivation layer overlying said entire integrated circuit structure, wherein said pattern of said patterned nitride passivation layer is formed such that openings in said patterned nitride passivation layer, each defining an area approximately equal to the area defined by the underlying gate oxide layer, overlay said thin gate oxide layer area of one or more of said MOS devices.
-
Specification