Duplexer package

• US 5,561,406 A
• Filed: 03/29/1995
• Issued: 10/01/1996
• Est. Priority Date: 07/01/1994
• Status: Expired due to Term

• Current Assignee: Taiyo Yuden Company Limited (Taiyo Yuden Co)
• Original Assignee: Fujitsu Limited
• Inventors: Satoh, Yoshio, Ikata, Osamu, Ohmori, Hideki, Hirasawa, Nobuo
• Primary Examiner(s): Lee, Benny
• Assistant Examiner(s): GAMBINO, DARUIS
• Application Number:
  US08/412,318
• Time in Patent Office: 552 Days
• Field of Search: 333/126, 333/127, 333/128, 333/132, 333/133, 333/193-196, 333/185
• US Class Current: 333/126
• CPC Class Codes: H03H 9/0576 including surface acoustic wave [SAW] devices
• CPC Class Codes: H03H 9/72 Networks using surface acoustic waves
• CPC Class Codes: H03H 9/725 Duplexers
• CPC Class Codes: H04B 1/525 with means for reducing leakage of transmitter signal into the receiver

Abstract

A multilayer duplexer package is provided, which includes: two surface-acoustic-wave filter chips having different center pass band frequencies; and at least two phase matching circuits for matching the phase of one filter chip to that of the other filter chip, said phase matching circuits respectively comprising strip lines stacked one above another, and said strip lines each having a characteristic impedance higher than the characteristic impedance of an external circuit to be connected to the duplexer package.

Claims

1. A multilayer duplexer package comprising:

two surface-acoustic-wave filter chips having different center pass band frequencies; and

at least two phase matching circuits for matching the phase of one filter chip to that of the other filter chip,

said phase matching circuits respectively comprising strip lines stacked one above another, and

said strip lines each having a characteristic impedance higher than the characteristic impedance of an external circuit to be connected to the duplexer package.

2. A duplexer package as set forth in claim 1,

wherein the characteristic impedance of each of said strip lines is set to a value 1.11 (±

7%) times that of said external circuit.

3. A duplexer package as set forth in claim 1,

wherein said strip lines each have different widths at opposite ends thereof.

4. A duplexer package as set forth in claim 1,

wherein the characteristic impedance of each of said strip lines is set to a value 1.11 (±

7%) times that of said external circuit, and

said strip lines each have different widths at opposite ends thereof.

5. A duplexer package as set forth in claim 1, 2, 3 or 4, wherein said strip lines and said filter chips are formed in tiers.

6. A duplexer package as set forth in claim 1,

wherein said strip lines each have different widths at opposite ends thereof, further comprising:

a common signal terminal for connecting the external circuit thereto, and

said strip lines are each connected to the common signal terminal at one end thereof and to the corresponding filter chip at the other end thereof; and

said one end of each of said strip lines connected to the common signal terminal has a width narrower than that of said other end thereof connected to the filter chip, so that the width of said each strip line gradually narrows from said other end connected to the filter chip to said one end connected to the common signal terminal.

7. A duplexer package as set forth in claim 6, wherein said strip lines and said filter chips are formed in tiers.

8. A duplexer package as set forth in claim 1 or 2,

wherein said filter chips each comprise parallel surface-acoustic-wave resonators connected in parallel to a signal line which links the common signal terminal and one of the strip lines, and a serial surface-acoustic-wave resonator connected in series to said signal line, wherein the number of the ground terminals for duplexer package is greater than that of parallel surface-acoustic-wave resonators of the filter chips.

9. A duplexer package as set forth in claim 8,

wherein said parallel surface-acoustic-wave resonators each have at least two ground terminals.