Pyramid processor integrated circuit

• US 5,561,617 A
• Filed: 03/10/1995
• Issued: 10/01/1996
• Est. Priority Date: 12/11/1991
• Status: Expired due to Term

• Current Assignee: Sarnoff Corporation (SRI International, Inc.)
• Original Assignee: David Sarnoff Research Center, Inc.
• Inventors: van der Wal, Gooitzen S.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/402,402
• Time in Patent Office: 571 Days
• Field of Search: 364/724.05, 364/724.16, 364/724.13, 382/41, 382/49, 382/43, 382/27, 382/17, 382/54, 382/22, 358/160
• US Class Current: 708/308
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G06T 2207/20016 Hierarchical, coarse-to-fine, multiscale or multiresolution image processing; Pyramid transform
• CPC Class Codes: G06T 2207/20024 Filtering details
• CPC Class Codes: G06T 5/00 Image enhancement or restoration

Abstract

Multiresolution (pyramid) filtering is useful in image processing. An IC for implementing a variety of multiresolution filters includes a programmable, symmetric, and separable two-dimensional filter. The input signal to the filter can be an input signal applied to the IC or a combination of two such signals. Circuitry in the IC may be programmed to imply pixel values around the edges of the two-dimensional image signals processed by the filter. The filter provides an output signal as well as each of the unfiltered signals from a tapped delay line of a filter that combines successive lines of the image. The IC also includes an arithmetic and logic unit in which the filtered output signal may be combined with an unfiltered input signal or one of the unfiltered tap signals. If the filter is programmed to produce a Gaussian low-pass filtered image, this image, combined with image data from a center one of the filter taps produces a Laplacian function of the original image.

Claims

1. An integrated circuit suitable for processing a video signal, comprising:

means for receiving the video signal as a digital data input signal;

a digital filter, including a tapped delay line which includes a memory having a number of words sufficient to hold digital sample values of the digital data input signal, said sample values representing a plurality of lines of a video image, wherein the number of words used to hold the digital sample valued representing the lines of the video image is changed dynamically to accommodate changing numbers of samples in the lines based only on information in the video signal, said digital filter being configured to process the digital data input signal in accordance with a transfer function to produce a first filtered signal; and

a first arithmetic and logic unit coupled to receive the filtered signal and an unfiltered signal and responsive to a first control signal to selectively combine the filtered signal and the unfiltered signal to produce a second filtered signal;

wherein the first and second filtered signals represent the output of the integrated circuit.

2. A circuit according to claim 1 wherein the digital filter is configured to be programmed to effectively change the number of taps of the tapped delay line which are used, between respective odd and even numbers, responsive to a tap-number control signal provided by a control circuit.

3. An integrated circuit, comprising:

a digital filter, including a tapped delay line, configured to process a digital data input signal in accordance with a transfer function to produce a first filtered signal; and

a first arithmetic and logic unit coupled to receive the filtered signal and an unfiltered signal and responsive to a first control signal to selectively combine the filtered signal and the unfiltered signal to produce a second filtered signal; and

a second arithmetic and logic unit, coupled to receive first and second digital data signals and responsive to a second control signal, to selectively provide either the first digital data signal, the second digital data signal or an arithmetic combination of the first and second digital data signals as the digital data input signal of the digital filter;

wherein the first and second filtered signals represent the output of the integrated circuit.

4. A circuit according to claim 3, further comprising:

control means, responsive to a programing signal to generate the first and second control signals.

5. A circuit according to claim 4, wherein:

the filter includes programmable coefficient values; and

the control means is responsive to the programming signal to program the coefficient values.

6. A circuit according to claim 5 wherein the control means is responsive to the programing signal being in first and second states to program the coefficient values used by the filter to be symmetric and antisymmetric, respectively.

7. A circuit according to claim 5, wherein the digital filter has a kernel size defined by the number of said coefficient values and the control means is responsive to the programming signal to program the digital filter to effectively insert a zero-valued coefficient between successive ones of the programmable coefficient values to effectively increase the kernel size of the filter.

8. An integrated circuit, comprising:

means for receiving a digital data signal including a data signal component and a timing signal component which indicates that active data is present in the digital data signal;

a two-dimensional digital filter configured to process the data signal component of the digital data signal in accordance with a programmed transfer function to produce a first filtered signal;

means, coupled to the two-dimensional filter for delaying the timing signal component of the digital data signal to compensate for processing delays imposed by the two-dimensional filter on the data component of the digital data signal; and

output means for providing the filtered signal and the delayed timing signal at an output port of the integrated circuit.

9. A circuit according to claim 8 further including

first and second separable component filters, each having a respective tapped delay line.

10. A circuit according to claim 9 further including

control means, responsive to a programming signal to program first and second sets of coefficient values for the respective first and second separable component filters;

and

wherein the two-dimensional digital filter includes first and second sets of programmable coefficient values for the respective first and second separable component filters.

11. A circuit according to claim 10, wherein the digital data signal has first data values and last data values representing respective borders of the image represented by the digital data signal, said circuit further including edge processing means for implying pixel values before the first data values and after the last data values in each of the two dimensions of the digital data signal processed by the two-dimensional digital filter.

12. An integrated circuit, comprising:

means for receiving a digital data signal including a data signal component and a timing signal component which indicates that active data is present in the digital data signal;

a two-dimensional digital filter, being configured to process the data signal component of the digital data signal in accordance with a programmed transfer function to produce a first filtered signal, said digital filter including first and second separable component filters, each having a respective tapped delay line, wherein the tapped delay line of the first component filter includes;

memory means for sequentially reading and writing N-bit values, where each N-bit value includes M bytes, N and M being integers greater than 1; and

means, coupled to the memory means for shifting each of the N-bit values provided by the memory means by B bits to positions of different significance in the N bit value, where each B-bit value corresponds to a respectively different pixel value, between the time that the N-bit value is read from the memory means and the time that the N-bit value is written into the memory means;

control means, responsive to a programming signal to program first and second sets of coefficient values for the respective first and second separable component filters;

wherein the two-dimensional digital filter includes first and second sets of programmable coefficient values for the respective first and second separable component filters;

means, coupled to the two-dimensional filter for delaying the timing signal component of the digital data signal to compensate for processing delays imposed bY the two-dimensional filter on the data component of the digital data signal; and

output means for providing the filtered signal and the delayed timing signal at an output port of the integrated circuit;

wherein the digital data signal has first data values and last data values representing respective borders of the image represented by the digital data signal, said circuit further including edge processing means for implying pixel values before the first data values and after the last data values in each of the two dimensions of the digital data signal processed by the two-dimensional digital filter.

13. An integrated circuit, comprising:

means for receiving a digital data signal including a data signal component and a timing signal component;

a two-dimensional digital filter including first and second separable component filters, each having a respective tapped delay line and including first and second sets of programmable coefficient values for the respective first and second separable component filters, the two-dimensional digital filter being configured to process the data signal component of the digital data signal in accordance with a programmed transfer function to produce a first filtered signal, wherein the tapped delay line of the first component filter includes;

     1) memory means for sequentially reading and writing N-bit values, where each N-bit value includes M bytes, N and M being integers greater than 1; and

     2) means, coupled to the memory means for shifting the N-bit values provided bY the memory means by B bits, where each byte includes B bits, between the time that the N-bit value is read from the memory means and the time that the N-bit value is written into the memory means;

control means, responsive to a programming signal to program the first and second sets of coefficient values;

auxiliary input means for applying an auxiliary sampled data input signal; and

means, coupled to the auxiliary input means and to the two-dimensional digital filter, for combining each sample of the auxiliary signal with L less significant bits of each sample of the filtered signal where each sample of the filtered signal has K bits, K and L being integers and L being less than K;

edge processing means for implying pixel values before the first data values and after the last data values in each of the two dimensions of the digital data input signal processed by the two-dimensional digital filter;

means, coupled to the two-dimensional filter for delaying the timing signal component of the digital data signal to compensate for processing delays imposed by the two-dimensional filter on the data signal component of the digital data signal; and

output means for providing the filtered signal and the delayed timing signal at an output port of the integrated circuit.

14. An integrated circuit suitable for processing a video signal, comprising:

a semiconductor substrate having thereon a plurality of semiconductor devices, said devices forming;

means for receiving the video signal as a digital data input signal;

a digital filter, including a tapped delay line which includes a memory having a number of words sufficient to hold respective digital sample values of the digital data input signal, said sample values representing a plurality of lines of a video image, wherein the number of words used to hold the digital sample values representing the lines of the video image is changed dynamically to accommodate changing numbers of samples in the lines based only on information in the video signal, said digital filter being configured to process the digital data input signal in accordance with a transfer function to produce a first filtered signal; and

a first arithmetic and logic unit coupled to receive the filtered signal and an unfiltered signal and responsive to a first control signal to selectively combine the filtered signal and the unfiltered signal to produce a second filtered signal;

wherein the first and second filtered signals represent the output of the integrated circuit.

15. An integrated circuit comprising:

a digital filter, including a tapped delay line, configured to process a digital data input signal in accordance with a transfer function to produce a first filtered signal;

a first arithmetic and logic unit coupled to receive the filtered signal and an unfiltered signal and responsive to a first control signal to selectively combine the filtered signal and the unfiltered signal to produce a second filtered signal; and

a second arithmetic and logic unit, coupled to receive first and second digital data signals each of the first and second digital data signals having a respective timing signal component which indicates that active data is present in the respective first and second digital data signal, the arithmetic and logic unit including;

means responsive to a second control signal, to selectively provide either the first digital data signal, the second digital data signal or an arithmetic combination of the first and second digital data signals as the digital data input signal of the digital filter; and

means, responsive to the timing signal components of the respective first and second digital data signals, for generating a timing signal for the digital data input signal of the digital filter, the generated timing signal indicating that active data is present in the digital data input signal;

wherein the first and second filtered signals represent the output of the integrated circuit.

16. An integrated circuit according to claim 15, wherein:

the digital filter includes first and second mutually orthogonal component filters, each having a respective tapped delay line.

17. An integrated circuit according to claim 16, said devices further forming:

control means, responsive to a programming signal to generate the first and second control signals.

18. An integrated circuit according to claim 17, wherein:

the digital filter includes programmable coefficient values; and

the control means is responsive to the programming signal to program the coefficient values.

19. An integrated circuit according to claim 18 wherein the control means is responsive to the programming signal to program the coefficient values used by the filter to be one of symmetric and antisymmetric.

20. An integrated circuit according to claim 19, wherein the digital filter has a kernel size defined by the number of said coefficient values and the control means is responsive to the programming signals to program the digital filter to effectively insert a zero-valued coefficient between successive ones of the programmable coefficient values to effectively increase the kernel size of the filter.

21. An integrated circuit according to claim 16 wherein the digital filter may be programmed to effectively change the number of taps of the tapped delay line which are used, between respective odd and even numbers, responsive to a tap-number control signal provided by a control circuit.