Integrated memory cube structure

• US 5,561,622 A
• Filed: 09/13/1993
• Issued: 10/01/1996
• Est. Priority Date: 09/13/1993
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Hedberg, Erik L., Howell, Wayne J., Kalter, Howard L., Kelley, Gordon A. Jr.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/120,993
• Time in Patent Office: 1,114 Days
• Field of Search: 365/51, 365/52, 365/63, 257/686, 257/724, 257/777, 361/684, 361/735
• US Class Current: 365/51
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]

Abstract

An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N×M memory devices appears at the cube'"'"'s I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

Claims

1. An integrated memory cube which to external circuitry emulates a single memory chip architecture, said integrated memory cube comprising:

a combination memory chip and logic chip stack including

(i) N memory chips (wherein N≧

2) each having M storage devices (wherein M≧

2), along with two substantially parallel planar main surfaces and an edge surface,

(ii) a logic chip electrically connected to each of the N memory chips for coordinating external circuitry communication with the N×

M storage devices of the stack, said electrically connected logic chip and N memory chips having an integrated memory architecture that emulates to said external circuitry a single memory chip architecture with said N×

M storage devices, wherein said external circuitry addresses said stack through said logic chip as said single memory chip architecture, said logic chip also having two parallel planar main surfaces and an edge surface, and

(iii) at least one planar main surface of each chip in the stack being coupled to a planar main surface of an adjacent chip in the stack, the edge surfaces of the N memory chips and the edge surface of the logic chip aligning to form at least one side surface of the stack, said stack also having an end surface disposed parallel to the planar main surfaces of the chips in the stack.

10. The integrated memory cube of claim 1, wherein the logic chip includes logic means for holding each of said N memory chips of the stack in a sleep mode in response to a control command received from external circuitry.

11. The integrated memory cube of claim 1, wherein the logic chip is electrically connected to receive an address signal from external circuitry and wherein the logic chip includes logic means for decoding the address signal to identify at least one memory chip of the M memory chips having a memory device addressed by the address signal.

12. The integrated memory cube of claim 1, wherein the logic chip includes logic means for sequentially refreshing each of the N memory chips in the stack.

13. The integrated memory cube of claim 12, wherein the logic means for sequentially refreshing includes a counter connected to sequentially track which memory chip of said N memory chips in the stack is to be refreshed.

14. The integrated memory cube of claim 1, wherein the logic chip includes logic means for regulating a received voltage to an on-chip voltage for powering at a desired level.

15. The integrated memory cube of claim 1, wherein N equals four.

16. The integrated memory cube of claim 1, wherein the N memory chips each comprise a RAM chip.

17. The integrated memory cube of claim 1, wherein at least some of the N memory chips include transfer metallurgy extending to the at least one side surface of the stack, and wherein the integrated memory cube further comprises a metallization pattern disposed on the stack'"'"'s at least one side surface and electrically connecting the transfer metallurgy extending thereto.

18. The integrated memory cube of claim 17, wherein the metallization pattern disposed on the stack'"'"'s at least one side surface electrically connects with the transfer metallurgy extending to the at least one side surface of the stack via T-connects.

19. The integrated memory cube of claim 18, wherein the logic chip is disposed adjacent to the end surface of said stack and includes transfer metallurgy extending to the at least one side surface of the stack, and wherein the integrated memory cube further comprises a spacer layer covering the logic chip and having an edge aligned with the at least one side surface of the stack, the spacer layer having a width and thickness sufficient to allow T-connects between the transfer metallurgy on the logic chip extending to the at least one side surface of the stack and the metallization pattern disposed on the at least one side surface of the stack.

2. An integrated memory cube architecture comprising:

a combination memory chip and logic chip stack including

(i) N memory chips (wherein N≧

2) each having M storage devices (wherein M≧

2), along with two substantially parallel planar main surfaces and an edge surface,

(ii) a logic chip electrically connected to each of the N memory chips for coordinating external communication with the N memory chips of the stack, said logic chip also having two parallel planar main surfaces and an edge surface,

(iii) at least one planar main surface of each chip in the stack being coupled to a planar main surface of an adjacent chip in the stack, the edge surfaces of the N memory chips and the edge surface of the logic chip aligning to form at least one side surface of the stack, said stack also having an end surface disposed parallel to the planar main surfaces of the chips in the stack, and

(iv) wherein one of said two parallel planar main surfaces of said logic chip comprises an upper surface of the logic chip, and wherein said upper surface of the logic chip includes an array of contact pads, at least some of said contact pads of said array of contact pads comprising I/O contacts for external circuitry connection to the stack.

3. The integrated memory cube of claim 2, wherein the logic chip is disposed at an end of the stack such that the upper surface of the logic chip comprises the end surface of the stack.

4. The integrated memory cube of claim 3, further comprising a lead frame secured to the stack adjacent its end surface, said lead frame having an inner opening extending therethrough such that at least a portion of the array of contact pads on the upper surface of the logic chip remains exposed.

5. The integrated memory cube of claim 4, further comprising conventional wirebonding electrically connecting the lead frame and at least some of the exposed contact pads of the array of contact pads on the upper surface of the logic chip.

6. The integrated memory cube of claim 3, further comprising a spacer layer disposed on the end surface of the stack, said spacer layer having an inner opening extending therethrough and sized to expose at least a portion of the contact pads on the upper surface of the logic chip, said spacer layer having a thickness sufficient to allow formation of T-connects along the at least one side surface of the stack adjacent to the upper surface of the logic chip.

7. The integrated memory cube of claim 6, further comprising a lead frame secured to on exposed surface of the spacer layer, said lead frame also having an inner opening extending therethrough sized such that the contact pads exposed through the spacer layer are also exposed through the lead frame.

8. The integrated memory cube of claim 7, further comprising conventional wirebonding electrically connecting the lead frame and at least some of the exposed contact pads on the upper surface of the logic chip.

9. The integrated memory cube of claim 2, wherein at least two of said contact pads of said array of contact pads are electrically interconnected for logic function programming.

20. An integrated memory cube which emulates for external circuitry a single memory chip architecture, said integrated memory cube comprising:

N memory chips (wherein N≧

2) each having M storage devices (wherein M≧

2), each memory chip of said N memory chips comprising a first single chip memory architecture, said N memory chips being laminated together in a stack; and

a logic circuit electrically connected to each of the N memory chips for coordinating external circuitry communication with the N×

M storage devices of the stack, said electrically connected logic circuit and N memory chips having an integrated memory architecture which emulates for said external circuitry a second single chip memory architecture having N×

M storage devices, said second single chip memory architecture comprising a different memory chip architecture from said first single chip memory architecture of each of said N memory chips.

21. The integrated memory cube of claim 20, wherein said logic circuit comprises a logic chip laminated to said stack.

22. The integrated memory cube of claim 20, wherein said logic circuit comprises a memory controller.

23. An integrated multichip memory module which emulates to external circuitry a single chip memory architecture, said integrated multichip memory module comprising:

a memory subunit having N memory chips (wherein N≧

2), each memory chip of the memory subunit having M memory devices (wherein M≧

2), along with two substantially parallel planar main surfaces and an edge surface, at least one planar main surface of each memory chip being coupled to a planar main surface of an adjacent memory chip of the memory subunit such that said memory subunit has a stack structure; and

logic means electrically connected to each of the N memory chips for coordinating external circuitry communication with said N memory chips of said memory subunit such that an integrated memory architecture with said N×

M memory devices;

exists which appears to said external circuitry to comprise said single chip memory structure with N×

M memory devices.

24. The integrated multichip memory module of claim 23, wherein said logic means;

comprises a logic chip mechanically coupled to said memory subunit.

25. The integrated multichip memory module of claim 23, wherein said logic means includes means for holding said N memory chips of said memory subunit in a sleep mode in response to a control command received from external circuitry.

26. The integrated multichip memory module of claim 23, wherein said logic means is connected to receive an address signal for said single chip memory structure from said external circuitry and wherein said logic means includes means for decoding said address signal to identify at least one of said N memory chips of said memory subunit having an addressed memory device identified by the address signal.

27. The integrated multichip memory module of claim 23, wherein said logic means includes means for sequentially refreshing each of said N memory chips of said memory subunit.

28. The integrated multichip memory module of claim 27, wherein said means for sequentially refreshing includes a counter connected for sequentially tracking a last refreshed memory chip of said N memory chips in said memory subunit.

29. The integrated multichip memory module of claim 23, wherein said memory subunit is powered at a first voltage level and said logic means is powered at a second voltage level.