Expansion bus system for replicating an internal bus as an external bus with logical interrupts replacing physical interrupt lines

• US 5,561,772 A
• Filed: 07/26/1994
• Issued: 10/01/1996
• Est. Priority Date: 02/10/1993
• Status: Expired due to Fees

• Current Assignee: PDACO LIMITED
• Original Assignee: Elonex Technologies, Inc.
• Inventors: Kikinis, Dan, Dornier, Pascal, Jacobs, William S., Seiler, William J.
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US08/280,924
• Time in Patent Office: 798 Days
• Field of Search: 395/725, 395/275, 395/550, 395/800, 395/375, 395/700, 395/739, 395/309, 395/402, 395/281, 395/410, 395/292, 395/325, 395/133, 364/DIG. 1, 364/DIG. 2
• US Class Current: 710/300
• CPC Class Codes: F02B 2075/027 four
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G06K 15/00 Arrangements for producing a permanent visual presentation of the output data , e.g. computer output printersprinting or plotting combined with another operation, e.g. with conveying, G06K17/00
• CPC Class Codes: H04M 1/725 Cordless telephones user interfaces specially adapted therefor H04M1/724
• CPC Class Codes: H04M 3/42323 PBX's with CTI arrangements
• CPC Class Codes: H04N 1/00127 Connection or combination of a still picture apparatus with another apparatus, e.g. for storage, processing or transmission of still picture signals or of information associated with a still picture
• CPC Class Codes: H04N 1/00204 with a digital computer or a digital computer system, e.g. an internet server programmed control between transmitter and receiver or between image input and image output device H04N1/32561
• CPC Class Codes: H04N 1/00278 with a printing apparatus, e.g. a laser beam printer
• CPC Class Codes: H04N 1/0461 part of the apparatus being used in common for reading and reproducing simultaneous scanning of the original picture and the reproduced picture with a common scanning device H04N1/207
• CPC Class Codes: H04N 1/1135 for the main-scan only
• CPC Class Codes: H04N 1/12 using the sheet-feed movement or the medium-advance or the drum-rotation movement as the slow scanning component, e.g. arrangements for the main-scanningsheet-feed movement by translatory movement of a flat picture-bearing surface H04N1/1008; main-scanning using oscillating or rotating mirrors H04N1/113; using multi-element arrays H04N1/19
• CPC Class Codes: H04N 2201/001 Sharing resources, e.g. processing power or memory, with a connected apparatus or enhancing the capability of the still picture apparatus
• CPC Class Codes: H04N 2201/0074 Arrangements for the control of a still picture apparatus by the connected apparatus arrangements for the control of the connected apparatus by the still picture apparatus H04N2201/0013; control of image communication with the connected apparatus H04N2201/0015
• CPC Class Codes: H04N 2201/0081 Image reader H04N2201/0091 - H04N2201/0094 take precedence
• CPC Class Codes: H04N 2201/0082 Image hardcopy reproducer H04N2201/0091 - H04N2201/0094 take precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to "high" memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM, allowing various models and types of CPUs to be supported. In this aspect, supported CPUs are interchangeable in the system. In another aspect a default interface attaches to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.

Claims

1. A computer bus expansion system comprising:

an internal bus having data, address, and control lines, but no interrupt lines;

bus control circuitry coupled to the internal bus and to a central processing unit (CPU);

a first translator connected to the internal bus;

an intermediate bus of lesser width than the internal bus, and connected to the first translator;

a second translator connected to the intermediate bus; and

an expansion bus having the same number of lines as and equivalent signals to the internal bus, the expansion bus connected to the second translator;

wherein interrupts are addresses unique to specific peripheral devices, the addresses are translated from address lines of the expansion bus through the second translator to the intermediate bus, and through the first translator from the intermediate bus onto address lines of the internal bus, the translations transparent to system operating code, and wherein the bus control circuitry decodes the addresses to the CPU as interrupts specific to the associated peripheral devices.

2. A computer bus expansion system as in claim 1 further comprising a peripheral device connected to the expansion bus, the peripheral device adapted for issuing an interrupt as an address specific to the peripheral device on address lines of the expansion bus.

3. A computer bus expansion system as in claim 1 wherein the intermediate bus is a Centronics™

-type cable with 25-pin end connectors, and the first translator is adapted for operating as in industry-standard parallel port as well as adapted for operating as a bus translator transparent to system operating code.

4. A computer bus expansion system as in claim 1 wherein the internal and external buses are compressed buses wherein 32-bit addresses and 32-bit data are multiplexed on 32 lines.

5. A computer system comprising:

an internal bus having data, address, and control lines, but no interrupt lines;

bus control circuitry coupled to the internal bus and to a central processing unit (CPU);

system memory;

first peripheral ports connected to the internal bus and adapted for connecting peripheral devices;

a first translator connected to the internal bus;

an intermediate bus of lesser width than the internal bus, and connected to the first translator;

a second translator connected to the intermediate bus;

an expansion bus having the same number of lines as and equivalent signals to the internal bus, the expansion bus connected to the second translator; and

second peripheral ports connected to the expansion bus and adapted for connecting peripheral devices;

wherein interrupts are addresses unique to specific peripheral devices connected to the peripheral ports, and wherein addresses, data, and control signals are translated between the internal bus and the expansion bus through the first and second translators and the intermediate bus transparent to system operating code, and wherein the bus control circuitry decodes the addresses to the CPU as interrupts specific to the associated peripheral devices.

6. A computer system as in claim 5 further comprising peripheral devices connected to the internal bus and the expansion bus at peripheral ports, the peripheral devices adapted for issuing interrupts as addresses specific to the peripheral devices connected to the peripheral ports.

7. A computer system as in claim 5 wherein the intermediate bus is a Centronics™

-type cable with 25-pin end connectors, and the first translator is adapted for operating as in industry-standard parallel port as well as adapted for operating as a bus translator transparent to system operating code.

8. A computer system as in claim 5 wherein the internal and external buses are compressed buses wherein 32-bit addresses and 32-bit data are multiplexed on 32 lines.

9. A method for issuing an interrupt from a peripheral device coupled to a first bus external to a computer to a central processing unit (CPU) coupled to a second bus internal to the computer, wherein the first and second buses have the same number of lines and equivalent signals and each lack interrupt lines, the method comprising steps of:

(a) issuing an address on address lines of the first bus by the peripheral device, the address unique to the peripheral device;

(b) translating the address through a first translating circuit onto an intermediate bus of less width than the first and second buses;

(c) translating the address through a second translating circuit from the intermediate bus onto address lines of the second bus; and

(d) decoding the address as an interrupt specific to the peripheral device at control circuitry coupled to the second bus.

10. The method of claim 9 wherein peripheral devices are connected to the internal bus and the expansion bus at peripheral ports, the peripheral devices adapted for issuing interrupts as addresses specific to the peripheral devices connected to the peripheral ports.

11. The method of claim 9 wherein the intermediate bus is a Centronics™

-type cable with 25-pin end connectors, and the first translator is adapted for operating as in industry-standard parallel port as well as adapted for operating as a bus translator transparent to system operating code.

12. The method of claim 9 wherein the internal and external buses are compressed buses wherein 32-bit addresses and 32-bit data are multiplexed on 32 lines.