Expansion bus system for replicating an internal bus as an external bus with logical interrupts replacing physical interrupt lines
First Claim
1. A computer bus expansion system comprising:
- an internal bus having data, address, and control lines, but no interrupt lines;
bus control circuitry coupled to the internal bus and to a central processing unit (CPU);
a first translator connected to the internal bus;
an intermediate bus of lesser width than the internal bus, and connected to the first translator;
a second translator connected to the intermediate bus; and
an expansion bus having the same number of lines as and equivalent signals to the internal bus, the expansion bus connected to the second translator;
wherein interrupts are addresses unique to specific peripheral devices, the addresses are translated from address lines of the expansion bus through the second translator to the intermediate bus, and through the first translator from the intermediate bus onto address lines of the internal bus, the translations transparent to system operating code, and wherein the bus control circuitry decodes the addresses to the CPU as interrupts specific to the associated peripheral devices.
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Accused Products
Abstract
A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to "high" memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM, allowing various models and types of CPUs to be supported. In this aspect, supported CPUs are interchangeable in the system. In another aspect a default interface attaches to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.
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Citations
12 Claims
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1. A computer bus expansion system comprising:
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an internal bus having data, address, and control lines, but no interrupt lines; bus control circuitry coupled to the internal bus and to a central processing unit (CPU); a first translator connected to the internal bus; an intermediate bus of lesser width than the internal bus, and connected to the first translator; a second translator connected to the intermediate bus; and an expansion bus having the same number of lines as and equivalent signals to the internal bus, the expansion bus connected to the second translator; wherein interrupts are addresses unique to specific peripheral devices, the addresses are translated from address lines of the expansion bus through the second translator to the intermediate bus, and through the first translator from the intermediate bus onto address lines of the internal bus, the translations transparent to system operating code, and wherein the bus control circuitry decodes the addresses to the CPU as interrupts specific to the associated peripheral devices. - View Dependent Claims (2, 3, 4)
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5. A computer system comprising:
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an internal bus having data, address, and control lines, but no interrupt lines; bus control circuitry coupled to the internal bus and to a central processing unit (CPU); system memory; first peripheral ports connected to the internal bus and adapted for connecting peripheral devices; a first translator connected to the internal bus; an intermediate bus of lesser width than the internal bus, and connected to the first translator; a second translator connected to the intermediate bus; an expansion bus having the same number of lines as and equivalent signals to the internal bus, the expansion bus connected to the second translator; and second peripheral ports connected to the expansion bus and adapted for connecting peripheral devices; wherein interrupts are addresses unique to specific peripheral devices connected to the peripheral ports, and wherein addresses, data, and control signals are translated between the internal bus and the expansion bus through the first and second translators and the intermediate bus transparent to system operating code, and wherein the bus control circuitry decodes the addresses to the CPU as interrupts specific to the associated peripheral devices. - View Dependent Claims (6, 7, 8)
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9. A method for issuing an interrupt from a peripheral device coupled to a first bus external to a computer to a central processing unit (CPU) coupled to a second bus internal to the computer, wherein the first and second buses have the same number of lines and equivalent signals and each lack interrupt lines, the method comprising steps of:
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(a) issuing an address on address lines of the first bus by the peripheral device, the address unique to the peripheral device; (b) translating the address through a first translating circuit onto an intermediate bus of less width than the first and second buses; (c) translating the address through a second translating circuit from the intermediate bus onto address lines of the second bus; and (d) decoding the address as an interrupt specific to the peripheral device at control circuitry coupled to the second bus. - View Dependent Claims (10, 11, 12)
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Specification