Power bus having power slits and holes embodied therein, and method for making the same

• US 5,561,789 A
• Filed: 05/31/1995
• Issued: 10/01/1996
• Est. Priority Date: 02/10/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Hoang, Hy, Chuang, Tatao, Long, Tran, Lin, Chong M.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/455,133
• Time in Patent Office: 489 Days
• Field of Search: 364/491, 364/488, 364/490, 364/489, 364/437, 395/750, 340/910, 324/754, 324/73.1, 361/794, 361/771, 361/683, 361/778, 361/805, 257/204, 257/207, 257/50, 257/52, 257/530, 365/19, 365/33, 365/44, 439/510, 345/69, 345/211
• US Class Current: 257/207
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An intersect area of an apparatus having a plurality of power buses, and a method for making the same. An intersect area is defined by an overlap region where a first and second power bus overlap. The power buses can overlap at orthogonal and non-orthogonal angles. Each power bus has a vertical and horizontal axis, along which power flows. Power slits are located along two axes. The intersect area of the apparatus is void of power slits, but has holes at intersection points of a set of pointer lines. The pointer lines are imaginary lines emanating from the power slits.

Claims

1. An apparatus comprising a pair of buses that intersect to form an intersect area, wherein said pair of buses have first and second power slits, respectively, said intersect area having holes formed therein, the location of said holes allowing electrons to flow through said pair of buses in an efficient manner.

2. The apparatus of claim 1, wherein the location of said holes is determined by the intersection of first and second pointer lines extending through said intersect area from said first and second power slits, respectively.

3. The apparatus of claim 1, wherein said first and second power buses intersect orthogonally.

4. The apparatus of claim 1, wherein said first and second power buses intersect in a non-orthogonal manner.

5. The apparatus of claim 4, wherein said first and second pointer lines extend in vertical and horizontal directions.

6. A method for generating holes in an intersect area defined by the intersection of a pair of buses, wherein the pair of buses have power slits formed therein, comprising the steps of:

(a) removing all power slits in the intersect area;

(b) extending first pointer lines from first power slits of a first bus to an opposite boundary side of the intersect area to connect the first power slits of the first bus;

(c) extending second pointer lines from second power slits of a second bus to an opposite boundary side of the intersect area to connect the second power slits of the second bus;

(d) intersecting, logically, the first pointer lines with the second pointer lines forming defined holes indicating where to generate power slits; and

(e) generating said power slits where the defined holes are located.

7. A method according to claim 6, wherein said step (e) comprises logically ANDing said first pointer lines with said second pointer lines to form the defined holes where said power slits are generated.

8. A method according to claim 6, wherein said step (b) comprises extending said first pointer lines in a vertical direction.

9. A method according to claim 6, wherein said step (b) comprises extending said first pointer lines in a horizontal direction.

10. A method according to claim 6, wherein said step (c) comprises extending said second pointer lines in a vertical direction.

11. A method according to claim 6, wherein said step (c) comprises extending said second pointer lines in a horizontal direction.