Method of securely controlling direct memory access (DMA) of a shared memory by a DMA device on an expansion board

• US 5,561,817 A
• Filed: 08/16/1993
• Issued: 10/01/1996
• Est. Priority Date: 08/16/1993
• Status: Expired due to Fees

• Current Assignee: Westinghouse Electric Company LLC (Brookfield Asset Management Incorporated)
• Original Assignee: Thermo King Corporation (Trane Technologies plc)
• Inventors: Johnson, Dannis R., McCormack, Michael D., Jurewicz, Romuald M.
• Primary Examiner(s): Gossage, Glenn
• Assistant Examiner(s): Etienne, Ario
• Application Number:
  US08/106,851
• Time in Patent Office: 1,142 Days
• Field of Search: 395/400, 395/425, 395/325, 395/842, 395/822, 395/826, 395/828, 395/846, 395/402, 395/882, 395/728, 395/186, 395/848, 395/475, 395/280, 395/281, 395/282
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A method of securely controlling direct memory access (DMA) in a microprocessor controlled system having a CPU on a CPU board which has an address/data bus connector for selectively connecting an expansion board to the CPU board, and a random access memory (RAM) on the CPU board having a specific address range which is accessible by a DMA device on the expansion board when the CPU board relinquishes control of the address/data bus to the DMA device in response to a bus access request. The method includes the steps of providing a plurality of logic signals, including a first logic signal having logic levels which indicate whether or not the CPU board is in control of the address/data bus, providing memory select signals for selecting different memory address ranges which are true in response to different Boolean equations each comprising predetermined combinations of predetermined logic signals, and including the first signal in the Boolean equation of at least one of the memory select signals, such that the at least one memory select signal can only be driven to a true level when the logic level of the first logic signal indicates that the CPU board is in control of the address/data bus. The method may be used to control DMA in a refrigeration related process or system.

Claims

1. A method of securely controlling direct memory access (DMA) in a microprocessor controlled system having a CPU on a CPU board which has an address/data bus, means for selectively connecting an expansion board to the CPU board, and a random access memory (RAM) on the CPU board having a specific address range which is accessible by a DMA device on the expansion board after the CPU board relinquishes control of the address/data bus to the DMA device in response to a bus access request, comprising the steps of:

providing a plurality of logic signals, including the step of providing a first logic signal having logic levels which indicate whether or not the CPU board is in control of the address/data bus,

providing memory select signals for selecting different memory address ranges which are true in response to different Boolean equations each comprising predetermined combinations of predetermined logic signals,

including said first logic signal in the Boolean equation of at least one of the memory select signals, with the included first logic signal having the logic level which indicates the CPU board is in control of the address/data bus, such that the at least one of the memory select signals can only be driven to a true level when the CPU board is in control of the address/data bus,

providing a second logic signal having logic levels which indicate whether or not an expansion board is connected to the CPU board,

and including said second logic signal in the Boolean equation of each memory select signal associated with a memory address range to which DMA is denied, with the included second logic signal having logic levels selected such that certain of the memory select signals can only be driven to a true level when the logic level of the second logic signal indicates that there is no expansion board attached to the CPU board, and the at least one memory select signal can only be driven to a true level when the second and first logic signals respectively indicate that an expansion board is connected to the CPU board, and that the CPU board is in control of the address/data bus.

2. The method of claim 1 including the step of providing at least one memory select signal which selects an address range for which DMA is allowed, and including the step of excluding the first logic signal from that at least one memory select signal.

3. The method of claim 1 including the step of providing at least one memory select signal which selects an address range for which DMA is allowed, and including the step of excluding the first and second logic signals from that at least one memory select signal.

4. The method of claim 1, wherein the method is used to control DMA in a microprocessor controlled refrigeration system.

5. A method of securely controlling direct memory access (DMA) in a microprocessor controlled system having a CPU on a CPU board which has an address/data bus, means for selectively connecting an expansion board to the CPU board, and a random access memory (RAM) on the CPU board having a specific address range which is accessible by a DMA device on the expansion board after the CPU board relinquishes control of the address/data bus to the DMA device in response to a bus access request, comprising the steps of:

providing a plurality of logic signals, including the step of providing a first logic signal having logic levels which indicate whether or not the CPU board is in control of the address/data bus,

providing memory select signals for selecting different memory address ranges which are true in response to different Boolean equations each comprising predetermined combinations of predetermined logic signals,

including said first logic signal in the Boolean equation of at least one of the memory select signals, with the included first logic signal having the logic level which indicates the CPU board is in control of the address/data bus, such that the at least one of the memory select signals can only be driven to a true level when the CPU board is in control of the address/data bus,

providing a second logic signal having logic levels which indicate whether or not an expansion board is connected to the CPU board,

including said second logic signal in the Boolean equation of each memory select signal associated with a memory address range to which DMA is denied,

providing a first type of Boolean equation which requires said second logic signal to be at a level which indicates no expansion board is attached in order to be driven to a true level,

providing a second type of Boolean equation which requires said second signal to be at a level which indicates an expansion board is attached in order to be driven to a true level,

and including the step of including the first logic signal in each of said second type of Boolean equations,

wherein the second type of Boolean equation can only be driven to a true level when the second and first logic signals respectively indicate that an expansion board is connected to the CPU board, and that the CPU board is in control of the address/data bus.

6. The method of claim 5 including the step of providing at least one memory select signal which selects an address range for which DMA is allowed, and including the step of excluding the first logic signal from that at least one memory select signal.

7. The method of claim 5 including the step of providing at least one memory select signal which selects an address range for which DMA is allowed, and including the step of excluding the first and second logic signals from that at least one memory select signal.

8. The method of claim 5, wherein the method is used to control DMA in a microprocessor controlled refrigeration system.