Method of making a field effect transistor

• US 5,563,079 A
• Filed: 06/09/1993
• Issued: 10/08/1996
• Est. Priority Date: 06/09/1992
• Status: Expired due to Fees

• Current Assignee: Goldstar Jewellery LLC
• Original Assignee: Goldstar Jewellery LLC
• Inventors: Kwon, Young S., Shin, Jin H., Kim, Chang T.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US08/073,428
• Time in Patent Office: 1,217 Days
• Field of Search: 437/912, 437/40, 437/41, 437/44, 437/944, 437/228 S, 437/40 SH, 437/40 RG, 257/267, 257/283, 257/330, 257/332
• US Class Current: 438/571
• CPC Class Codes: H01L 21/0272 for lift-off processes
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/28581 Deposition of Schottky electrodes
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 29/66863 Lateral single gate transistors

Abstract

A method of making a FET includes the steps of forming a source and a drain at respective edges of the surface of a semiconductor substrate, forming a first insulation film on the whole surfaces of the semiconductor substrate, the source, and the drain, coating a photoresist on the first insulation film, patterning the photoresist using a photolithography process to form a photoresist pattern having a first space corresponding to a gate length between the source and the drain, forming a second insulating film on the whole surfaces of the exposed first insulation film and the photoresist pattern, etching the second insulation film to form sidewall insulation films at the sidewalls of the photoresist patterns, etching the first insulation film using the sidewall insulation films and the photoresist pattern as an etching mask to form first insulation film patterns, which form a second space having a width smaller than that of the first space, beneath the first space, removing the sidewall insulation films to form a T-shaped space, and depositing a conductor to form a T-shaped gate in the T-shaped space.

Claims

1. A method of making an FET having a semiconductor substrate, a source, and a drain, the method comprising the steps of:

(a) forming the source and the drain at respective locations on a surface of the semiconductor substrate;

(b) forming a first insulation film on said surface of the semiconductor substrate and the source and the drain;

(c) coating a photoresist on the first insulation film;

(d) patterning the photoresist using a photolithography process to form a photoresist pattern, an edge portion of said photoresist pattern having sidewalls defining a first space, said first space exposing a portion of said first insulation film corresponding to a gate length between the source and the drain;

(e) forming a second insulating film on said exposed portion of the first insulation film and the patterned photoresist including said sidewalls of said patterned photoresist;

(f) etching the second insulation film to form sidewall insulation films at said sidewalls of the patterned photoresist defining the first space;

(g) etching the first insulation film using the sidewall insulation films and the photoresist pattern as an etching mask to form first insulation film patterns, said first insulation film patterns forming a second space beneath the first space, the second space having a width smaller than a width of the first space;

(h) removing the sidewall insulation films to form a T-shaped space;

(i) depositing a conductive material to form a T-shaped gate in the T-shaped space, said conductive material also being deposited on said patterned photoresist;

(j) removing the patterned photoresist and said conductive material deposited on the patterned photoresist after forming the T-shaped gate; and

(k) removing the first insulation film patterns.

2. A method in accordance with claim 1, further comprising the step of:

(l) forming a third insulation film serving as a protection film on an exposed portion of the substrate, the source, the drain and the T-shaped gate.

3. A method in accordance with claim 1, wherein the removing step (j) is carried out using a lift-off process.

4. A method in accordance with claim 1, further comprising a step of performing a heat-treatment process to harden the first insulation film between the step(b) and the step (c).

5. A method in accordance with claim 1, wherein the first insulation film is formed with an etch selectivity higher than that of the second insulation film.

6. A method in accordance with claim 1, wherein the first insulation film is made of one of a photoresist and a polyimide.

7. A method in accordance with claim 1, wherein the etching step (f) is carried out by an RIE method.

8. A method in accordance with claim 7, wherein the RIE method uses CF₄ as an etch gas.

9. A method in accordance with claim 1, wherein the second insulation film is formed using one of a sputtering method and a PECVD method.

10. A method in accordance with claim 1, wherein the sidewall insulation films are removed by an HF solution.

11. A method in accordance with claim 1, wherein the second insulation film is made of SiO₂.

12. A method in accordance with claim 1, wherein the gate is made of one of a metal and a polysilicon having a conductivity type.