Method of fabricating non-volatile sidewall memory cell

• US 5,563,083 A
• Filed: 04/21/1995
• Issued: 10/08/1996
• Est. Priority Date: 06/17/1994
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Pein, Howard B.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/426,512
• Time in Patent Office: 536 Days
• Field of Search: 437/43, 437/67, 437/49, 148/DIG. 50
• US Class Current: 438/259
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 148/05 Etch and refill

Abstract

A non-volatile memory cell and array of such cells is provided. The memory cell includes a single transistor floating gate cell fabricated on a sidewall of a silicon pillar etched into a silicon substrate. The memory cells are arranged in an array of rows extending in a bit line direction and columns extending in a word line direction. A substantially smaller cell and array size is realized by limiting the dimension of the pillar and the bit line in the word line direction to be the minimum line width as limited by the lithography.

Claims

1. A method of forming a non-volatile memory in a silicon substrate of a first conductivity type, said memory including a plurality of pillars arranged in an array of rows extending in a bit line direction and columns extending in a word line direction, said method comprising the steps of:

forming said plurality of pillars in said substrate whereby a dimension of each pillar in said word line direction and between each of said pillars in a column is a minimum line width, each of said pillars being of a first conductivity type;

growing a first dielectric layer on said substrate;

forming a floating gate around each pillar separated from said pillar by said first dielectric layer;

implanting an impurity of a second conductivity type to form a drain region on a top of each of said pillars and a single source region in said substrate;

growing a second dielectric layer on said substrate;

forming a continuous control gate around each floating gate in each word line row separated from said floating gate by said second dielectric layer; and

forming a bit line for each row having a dimension in said word line direction equal to said minimum line width, said bit line contacting said drain region of each pillar of said row.

2. The method of claim 1, wherein the step of forming said plurality of pillars includes etching said pillars anisotropically in said substrate.

3. The method of claim 1, wherein the step of forming said floating gate includes depositing polysilicon over said first dielectric layer and then etching said deposited polysilicon to form said floating gate around each of said pillars.

4. The method of claim 1, further including the step of forming a control gate contact for each control gate by extending one of said pillars in a column.

5. The method of claim 1, wherein the step of forming a bit line includes depositing a further dielectric layer over said array, etching a trench to expose said tops of said pillars in one of said rows, depositing metal over the array and etching back said metal so that said metal remains only in said trench.

6. A memory made by the method of claim 1.

7. A memory made by the method of claim 5.