Method of making a three-dimensional integrated circuit

• US 5,563,084 A
• Filed: 09/22/1995
• Issued: 10/08/1996
• Est. Priority Date: 09/22/1994
• Status: Expired due to Term

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Buchner, Reinhold, Ramm, Peter
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/532,858
• Time in Patent Office: 382 Days
• Field of Search: 437/51, 437/52, 437/59, 437/8, 437/56, 437/208, 437/226, 437/974, 148/DIG. 135
• US Class Current: 438/15
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/135 Removal of substrate
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method of making a three dimensionally integrated circuit by connecting first and second substrates (1;7) provided with devices in at least one layer in at least one surface in each of said substrates. An auxiliary substrate is connected to the one surface of one of said substrates which is then reduced in thickness from its opposite surface. The auxiliary layer with the devices thereon is then separated into individual chips which after having been found to be functioning are aligned and mounted in a side-by-side arrangement on said one surface of said first substrate. Electrical connection are formed between the devices of the mounted chips and the devices in the first substrate.

Claims

1. A method of making a three-dimensionally integrated circuit, comprising the steps of:

a) providing a first substrate provided at a first surface with at least one fully processed first device layer (3) having a plurality of independent devices arranged in a side-by-side relationship therein;

b) providing a second substrate provided at one of its surfaces with at least one fully processed second device layer having a plurality of independent devices arranged in a side-by-side relationship therein, said devices having been tested for their functionality;

c) connecting said one surface of said second substrate to an auxiliary substrate;

d) reducing the thickness of said second substrate from a surface opposite its said one surface;

e) separating said auxiliary substrate and said devices in said second device layer into individual chips respectively containing functioning and defective devices;

f) aligning and mounting chips containing functioning devices in a side-by-side arrangement on said first surface of said first substrate whereby moats are created between said mounted chips;

g) removing said auxiliary substrate;

h) planarizing said moats between said mounted chips;

i) forming electrical interconnections between said devices of said mounted chips and said devices in said first device layer.

2. The method of claim 1, wherein said first and said one surface of said first and second substrates each contain one device layer.

3. The method of claim 1, wherein said devices include circuit structures.

4. The method of claim 3, wherein said first and said one surface each contain a plurality of device layers and wherein said devices and said circuit structures in said pluralities of said first and second device layers form device stacks.

5. The method of claim 1, wherein said steps of aligning and mounting said chips and of forming said electrical contacts are performed simultaneously.

6. The method of claim 4, wherein said step of providing said second substrate further comprises the step of testing said devices in said device layers of said second substrate for their functionality.

7. The method of claim 4, wherein said first substrate comprises a three dimensionally integrated circuit made by the method of claim 1 and further comprising the step of adding thereto at least one more substrate repeating steps b) through i) of claim 1.

8. The method of claim 1, wherein said auxiliary substrate is connected to said one surface by a first adhesion layer.

9. The method of claim 8, wherein said chips are mounted on said first surface by a second adhesion layer.

10. The method of claim 9, wherein said adhesion layers effect passivation of said first and said one surface.

11. The method of claim 9, wherein said adhesion layer effects a planarization of said first and said one surface.

12. The method of claim 1, wherein said electrical interconnections between said devices in said first and second substrates are formed through passage means in said first and second substrates.

13. The method of claim 12, wherein said passage means comprises via holes.

14. The method of claim 13, wherein said passage means further comprises contact apertures.

15. The method of claim 1, wherein said step of reducing the thickness of said second substrate comprising an etching process.

16. The method of claim 1, wherein said step of reducing the thickness of said second substrate comprises a grinding process.

17. The method of claim 1, wherein said second substrate comprises a silicon-on-insulator (SOI) substrate.