Rugged CMOS output stage design

• US 5,563,438 A
• Filed: 10/26/1994
• Issued: 10/08/1996
• Est. Priority Date: 10/26/1994
• Status: Expired due to Fees

• Current Assignee: Alliedsignal Inc.
• Original Assignee: Alliedsignal Inc.
• Inventors: Tsang, Joseph C.
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): BOWERS, COURTNEY
• Application Number:
  US08/329,753
• Time in Patent Office: 713 Days
• Field of Search: 257/373, 257/328, 257/356, 257/357, 257/355, 257/343, 257/401
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A rugged MOS output stage transistor having a third region formed adjacent to the drain region on the side opposite the source. The third region is doped to have a polarity opposite the drain and forms in combination with the drain an output protect diode which renders the transistor relatively free of latch-up. The concept of the third region of opposite polarity adjacent to the drain may be used in both NMOSFET and PMOSFET as well as CMOS output stages.

Claims

1. A rugged CMOS output stage comprising:

a silicon substrate;

a P well provided in said substrate;

a first source region provided in said P well;

an N⁺ drain region provided in said P well spaced from said first source;

a first gate provided on a surface of said substrate intermediate said first source region and said N⁺ drain region;

a P region provided in said P well forming a junction with said N⁺ drain region on the side opposite said first source region, said P region being more highly doped than said P well and forming in conjunction with said N⁺ drain region an output protect diode, said first source region, said first gate and said N⁺ drain region are arranged in a first annular geometry with said P region being in the center of said first annular geometry;

at least one electrical contact to said N⁺ drain region located at a distance K from said first gate and at a distance L from said junction of said N⁺ drain region and said P region wherein the ratio between said distance K and said distance L is selected to cause an avalanche action to occur preferentially in said P region;

an N well provided in said substrate;

a second source region provided in said N well;

a P⁺ drain region provided in said N well spaced from said second source region;

a second gate disposed on the surface of said substrate intermediate said second source region and P⁺ drain region;

an N region provided in said N well forming a junction with said P⁺ drain region on the side opposite said second source region, said N region being more highly doped than said N well and forming in conjunction with said P⁺ drain region an output protect diode, said second source region, said second gate and said P⁺ drain region being arranged in a second annular geometry with said N region being in the center of said second annular geometry; and

at least one electrical contact to said P⁺ drain region located at said distance K from said second gate and said distance L from said junction of said P⁺ drain region and said N region wherein the ratio between said distance K and said distance L is selected to cause an avalanche action to preferentially occur in said N region.

2. The rugged CMOS output stage of claim 1 wherein said first and second sources comprise alternating N⁺ and P⁺ subregions adjacent to said first and second gates, respectively.

4. The rugged CMOS output stage of claim 1 wherein said at least one electrical contacts to said P⁺ and N⁺ drain regions respectively is a plurality of electrical contacts to said N⁺ and P⁺ drain regions located at said distance K from said gates, and located said distance L from the junction between said N⁺ drain region and said P region and from the junction between said P⁺ drain region and said N region and where said ratio of the distances K to L is greater than 1.

3. The rugged CMOS output stage of claim 8 wherein said first and second sources comprise alternating N⁺ an P⁺ subregions adjacent to said first and second gates, respectively.

5. The rugged CMOS output stage of claim 3 further including a first electrical connector electrically connecting said first gate and second gate to each other and to a common input tab, a second electrical connector connecting said alternating N⁺ and P⁺ subregions of said first source to each other and to a source voltage tab, a third electrical connector connecting said N⁺ drain to an output pad, a fourth connector connecting said alternating N⁺ and P⁺ subregions of said second source to a drain voltage input tab and a fifth connector connecting said P⁺ drain region to a second output pad.