Semiconductor device

• US 5,563,445 A
• Filed: 03/13/1995
• Issued: 10/08/1996
• Est. Priority Date: 04/08/1993
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Seki, Shigeaki, Iijima, Yoshitaka
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US08/351,383
• Time in Patent Office: 575 Days
• Field of Search: 257/780, 257/781, 257/786, 257/737, 257/738, 257/698, 257/692, 257/693
• US Class Current: 257/698
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/4554 Coating
• CPC Class Codes: H01L 2224/45644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/49572 consisting of thin flexible metallic tape with or without a film carrier H01L23/49503 - H01L23/49568 and H01L23/49575 - H01L23/49579 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor chip is positioned over the device hole of a circuit board which includes an insulating flexible substrate. The electrode bumps of the semiconductor chip are bonded to the lead portions of the conductive pattern, which protrude into the device hole by using the single-point bonding method. The circuit board includes superimposing areas of the substrate that overlie the semiconductor chip at the four corner areas of the device hole, as well as the superimposing area that divides the device hole into the four holes. Dummy bumps are provided on the areas of the semiconductor chip that overlap these superimposing areas. The dummy bumps are not to be bonded to the conductive pattern and are positioned between the circuit board and the semiconductor chip to maintain a specified distance between the two. Furthermore, a through-hole is provided in the superimposing area to allow air to escape when a molding agent is injected through the holes.

Claims

1. A circuit board for mounting thereon a semiconductor chip having a plurality of bonding electrode bumps, comprising:

an insulating substrate having a device hole over which the semiconductor chip is disposed, said substrate including a superimposing area extending in said device hole and dividing said device hole into a plurality of holes;

a conductive pattern formed on said substrate and having a plurality of lead portions that protrude into the device hole and are bonded to the electrode bumps of the semiconductor chip; and

a plurality of spacers formed on said superimposing area of said substrate and positioned between said substrate and the semiconductor chip, said spacers having a thickness that does not change after the lead portions of said conductive pattern and the electrode bumps of the chip are bonded together so as to maintain a predetermined distance between the circuit board and the semiconductor chip;

molding agent filled in said plurality of holes in said device hole.

2. The device of claim 1 wherein said spacers are dummy bumps.

3. The board of claim 1 wherein said device hole has an approximately quadrangular outline and said substrate further includes superimposing areas positioned at four corner areas of said device hole.

4. The board of claim 1 wherein said substrate further includes superimposing areas positioned along each side of said device hole.

5. The board of claim 1 wherein said substrate includes a superimposing area positioned inside said device hole, dividing said device hole into multiple holes.

6. The board of claim 1 wherein said superimposing area of said substrate extends through the approximate center of said device hole to divide said device hole into said plurality of holes.

7. The board of claim 6 wherein a portion of the superimposing area at the approximate center of said device hole includes a through hole.

8. The board of claim 6 wherein said conductive pattern includes a cross-over portion that traverses said device hole.

9. A semiconductor device, comprising:

a semiconductor chip having a plurality of bonding electrode bumps and spacers; and

a circuit board including;

an insulating substrate having a device hole over which said semiconductor chip is disposed, said substrate including a superimposing area extending in said device hole and dividing said device hole into a plurality of holes;

a conductive pattern formed on said substrate and having a plurality of lead portions that protrude into the device hole and are bonded to the electrode bumps of said semiconductor chip;

wherein said spacers of said semiconductor chip are positioned between said superimposing areas and said semiconductor chip, and said spacers having a thickness that does not change after the lead portions of said conductive pattern and the electrode bumps of said chip are bonded together so as to maintain a predetermined distance between said circuit board and said semiconductor chip;

molding agent filled in said plurality of holes in said device hole.

10. The device of claim 9 wherein said spacers are dummy bumps that are not bonded to said conductive pattern.

11. The device of claim 10 wherein portions of said conductive pattern on said superimposing area overlap said dummy bumps.

12. The device of claim 10 wherein said device hole has an approximately quadrangular outline and said substrate further includes superimposing areas positioned at four corner areas of said device hole.

13. The device of claim 10 wherein said substrate further includes superimposing areas positioned along each side of said device hole.

14. The device of claim 9 wherein said substrate includes a superimposing area positioned inside said device hole, dividing said device hole into multiple holes.

15. The device of claim 10 wherein said superimposing area of said substrate extends through the approximate center of said device hole to divide said device hole into said plurality of holes.

16. The device of claim 15 wherein a portion of the superimposing area at the approximate center of said device hole includes a through hole.

17. The device of claim 15 wherein said conductive pattern includes a cross-over portion that traverses said device hole.

18. A semiconductor device, comprising:

a semiconductor chip having a plurality of bonding electrode bumps; and

a circuit board including;

an insulating substrate having a device hole over which said semiconductor chip is disposed, said substrate including a superimposing area extending in said device hole and dividing said device hole into a plurality of holes;

a conductive pattern formed on said substrate and having a plurality of lead portions that protrude into the device hole and are bonded to the electrode bumps of said semiconductor chip; and

a plurality of spacers formed as protrusions of said conductive pattern and positioned between said conductive pattern and said semiconductor chip, and said spacers having a thickness that does not change after the lead portions of said conductive pattern and the electrode bumps of said chip are bonded together so as to maintain a predetermined distance between said circuit board and said semiconductor chip;

molding agent filled in said plurality of holes in said device hole.

19. The device of claim 18 wherein said semiconductor chip further includes dummy pads that overlap said spacers on said conductive pattern.

20. The device of claim 19 wherein said dummy pads of said chip include concave receptacles into which said spacers are disposed.

21. The device of claim 18 wherein said device hole has an approximately quadrangular outline and said substrate further includes superimposing areas positioned at four corner areas of said device hole.

22. The device of claim 18 wherein said substrate further includes superimposing areas positioned along each side of said device hole.

23. The device of claim 18 wherein said substrate includes a superimposing area positioned inside said device hole, dividing said device hole into multiple holes.

24. The device of claim 18 wherein said superimposing area of said substrate extends through the approximate center of said device hole to divide said device hole into said plurality of holes.

25. The device of claim 24 wherein a portion of the superimposing area at the approximate center of said device hole includes a through hole.

26. The device of claim 24 wherein said conductive pattern includes a cross-over portion that traverses said device hole.