Reducing current supplied to an integrated circuit

• US 5,563,499 A
• Filed: 06/29/1995
• Issued: 10/08/1996
• Est. Priority Date: 05/25/1993
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Pinney, David L.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): BERHANE, ADOLF D
• Application Number:
  US08/496,741
• Time in Patent Office: 467 Days
• Field of Search: 323/266, 323/224, 323/313, 323/267, 323/272, 327/530, 327/538
• US Class Current: 323/266
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

An integrated circuit of the present invention includes power regulating circuitry for reducing preregulator bias current. In one embodiment, power regulating circuitry includes a two stage preregulator for supplying current to a charge pump and a primary regulator. The first stage includes a high power operational amplifier for quickly establishing substrate bias and other pumped voltages before primary voltage is coupled to the remainder of the integrated circuit. Preregulated and pumped voltages are used to establish a reference voltage for the primary regulator. The second stage preregulator includes a low power series regulator to power the charge pumps and so maintain the reference voltage. When the primary regulator has generated the primary voltage level, the power regulating circuitry couples the primary voltage to the remainder of the integrated circuit and disables the first stage preregulator. Using circuitry and operating methods of the present invention, the total operating and standby current supplied to the integrated circuit no longer includes the bias currents related to the operation of the high power operational amplifier.

Claims

1. A voltage regulator for an integrated circuit device, comprising:

a first regulator portion coupled to a power supply input of the device, said first regulator portion having a control input and a first regulated voltage output;

a reference voltage source having a reference voltage output;

a second regulator portion coupled to the reference voltage output, said second regulator portion having a second regulated voltage output; and

a regulator power reduction circuit coupled to the control input and to the second regulated voltage output;

wherein said regulator power reduction circuit substantially inhibits said first regulator from receiving current from the power supply in response to the second regulated voltage output achieving a minimum value.

2. The voltage regulator of claim 1, wherein the fist regulated voltage output provides power to a first subcircuit of the device, and the second regulated voltage output provides power to a second subcircuit of the device.

3. The voltage regulator of claim 2, wherein the second regulated voltage output further provides power to the first subcircuit when said first regulator portion is inhibited from receiving current.

4. The voltage regulator of claim 2, further comprising;

a charge pump coupled to said first regulator portion, responsive to the first regulated voltage output to produce a third regulated voltage output.

5. The voltage regulator of claim 4, wherein the second regulated voltage output is enabled to provide power to the second subcircuit in response to the third regulated voltage output attaining a valid potential.

6. A voltage regulator comprising:

a current limiting circuit;

a preregulator coupled to a power source through said current limiting circuit;

a control circuit coupled to said current limiting circuit; and

a primary voltage regulator coupled to said control circuit, wherein said control circuit is responsive to said primary voltage regulator to limit current flow from the power source to said preregulator.

7. An integrated circuit device comprising:

a first voltage regulator coupled to an input power source of the device;

a first circuit coupled to said first voltage regulator;

a second voltage regulator coupled to the power source;

a second circuit coupled to said second voltage regulator;

a regulated power bus coupled to said first circuit and said second circuit; and

a current limiting control circuit coupled to said first voltage regulator and said regulated power bus, said current limiting control circuit adapted to restrict current from the power source to said first voltage regulator after a potential of said regulated power bus achieves a valid value.

8. The integrated circuit device of claim 7, wherein said first circuit is a charge pump which is adapted to pump a substrate of the device to a negative potential.

9. The integrated circuit device of claim 7 wherein said first circuit is a charge pump which is adapted to provide a regulated potential, above a potential of the input power source, on said regulated power bus.

10. The integrated circuit device of claim 7, wherein the device is a microprocessor.

11. The integrated circuit device of claim 7, wherein the device is a memory device.

12. The integrated circuit device of claim 7, wherein restriction of current by said current limiting control circuit causes a reduction of heat production by the device.

13. The integrated circuit device of claim 7, wherein restriction of current by said current limiting control circuit causes a reduction of power consumption of the device.

14. The integrated circuit device of claim 7, wherein said second circuit receives a regulated operating supply voltage from said second voltage regulator in response to said current limiting control circuit restricting current to said first voltage regulator.

15. An integrated circuit comprising:

a voltage regulator, coupled to an external power source, operable in a high power mode and a low power mode; and

a charge pump coupled to said voltage regulator and to a regulated voltage power bus;

wherein said voltage regulator is operated in the high power mode in response to the external power source, and said voltage regulator is operated in the low power mode after said charge pump produces a valid potential on the regulated voltage power bus.

16. The integrated circuit of claim 15, further comprising a memory array coupled to said charge pump.

17. A voltage regulator comprising:

a voltage reference circuit adapted to provide a reference potential;

a charge pump adapted to provide a regulated potential;

a control circuit responsive to the reference potential and the regulated potential to provide a bias potential; and

a transistor coupled to an external power source and to a regulated power bus, said transistor responsive to the bias potential to provide a regulated voltage on the regulated power bus.

18. A voltage regulator for an integrated circuit, comprising:

a first regulator portion coupled to a power supply input of the integrated circuit, said first regulator portion having a control input and a first regulated voltage output;

a second regulator portion coupled to the power supply input, said second regulator portion having a second regulated voltage output;

a charge pump having a third regulated voltage output; and

a regulator power reduction circuit coupled to the control input and to the third regulated voltage output;

wherein said regulator power reduction circuit enables said first regulator to receive current from the power supply in response to an invalid level of said third regulated voltage.

19. The regulator of claim 18, further comprising:

a regulated power bus coupled to the first regulated voltage output and the second regulated voltage output; and

a subcircuit coupled to said regulated power bus.

20. A portable computer comprising:

a battery; and

an integrated circuit comprising;

a voltage regulator, coupled to said battery, operable in a high power mode and a low power mode; and

a charge pump coupled to said voltage regulator and to a regulated voltage power bus;

wherein said voltage regulator is operated in the high power mode in response to a power signal of said battery, and said voltage regulator is operated in the low power mode after said charge pump produces a valid potential on the regulated voltage power bus.

21. An electrical system comprising:

a battery;

a first voltage regulator coupled to said battery;

a first circuit coupled to said first voltage regulator;

a second voltage regulator coupled to said battery;

a second circuit coupled to said second voltage regulator;

a regulated power bus coupled to said first circuit and said second circuit; and

a current limiting control circuit coupled to said first voltage regulator and said regulated power bus, said current limiting control circuit adapted to restrict current from the battery to said first voltage regulator after a potential of said regulated power bus achieves a valid value.

22. The electrical system of claim 21, wherein a memory device of the system comprises said first voltage regulator, said first circuit, said second voltage regulator, said second circuit, said regulated power bus and said current limiting control circuit.

23. A method of supplying regulated power to a circuit, comprising steps of:

supplying current to a high power voltage regulator;

generating a first regulated voltage through the high power voltage regulator;

generating a second regulated voltage in a charge pump;

generating a third regulated voltage;

supplying the second regulated voltage to the circuit;

detecting a valid potential level of the third regulated voltage;

reducing current supplied to the high power voltage regulator in response to said step of detecting; and

supplying the third regulated voltage to the circuit.

24. The method of claim 23, further comprising a step of:

generating a voltage reference from a band gap reference circuit.

25. The method of claim 23, wherein said step of supplying the third regulated voltage is performed after said step of detecting a valid potential.

26. The method of claim 23 wherein the first regulated voltage and the third regulated voltage are each in a range of approximately 3 volts to approximately 3.3 volts.

27. The method of claim 23 wherein the third regulated voltage is greater than one threshold voltage above the first regulated voltage.

28. An integrated circuit, comprising:

a first regulator coupled to a power supply input of the integrated circuit, said first regulator coupled to a first regulated voltage bus;

a charge pump adapted to provide a pumped potential greater than a potential of the power supply input;

a second regulator responsive to the pumped potential to supply current to a second regulated voltage bus; and

a low power regulator coupled to the first regulated voltage bus, wherein said low power regulator provides a regulated voltage on the first regulated voltage bus in response to the pumped potential.

29. The integrated circuit of claim 28, wherein current from the power supply input to the first regulator portion is restricted in response to the pumped potential.