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Process independent design for gate array devices

  • US 5,563,801 A
  • Filed: 10/06/1993
  • Issued: 10/08/1996
  • Est. Priority Date: 10/06/1993
  • Status: Expired due to Term
First Claim
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1. A method of manufacturing an integrated circuit to perform a specified function, comprising the steps of:

  • generating information corresponding to an electronic circuit designed to perform the specified function;

    determining characteristics of an integrated circuit fabricated using a first integrated circuit fabrication process, said characteristics including speed;

    establishing a general pattern for an integrated circuit, within which pattern will be placed specific circuit elements;

    developing a first layout for said integrated circuit, said first layout including location information for each transistor of said integrated circuit within said general pattern, wherein said developing step is performed using the information corresponding to the electronic circuit configured to perform the specified function and information corresponding to a first type integrated circuit fabrication process;

    determining characteristics of an integrated circuit fabricated using a second integrated circuit fabrication process, said characteristics including speed;

    determining differences in characteristics between an integrated circuit fabricated using said first fabrication process and an integrated circuit fabricated using said second fabrication process;

    developing a second layout for said integrated circuit, said second layout including location information for each transistor of said integrated circuit within said general pattern, wherein said developing step is performed using the information corresponding to the electronic circuit configured to perform the specified function, information corresponding to a second type integrated circuit fabrication process, and information corresponding to said first type integrated circuit fabrication process, and including the step of adjusting channel widths of transistors in said second layout based upon said differences in characteristics between an integrated circuit fabricated using said first fabrication process and an integrated circuit fabricated using said second fabrication process.

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