Method and apparatus for searching for data in multi-bit flash EEPROM memory arrays

• US 5,563,828 A
• Filed: 12/27/1994
• Issued: 10/08/1996
• Est. Priority Date: 12/27/1994
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gould, Geoff, Hasbun, Robert
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/364,619
• Time in Patent Office: 651 Days
• Field of Search: 365/45, 365/900, 365/218, 365/185.33
• US Class Current: 365/185.33
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 15/046 using non-volatile storage elements

Abstract

An arrangement which provides for searching for a data pattern in a flash EEPROM memory array using the internal controllers of the individual chips of the array. By utilizing these controllers to conduct the search, an external database is not required to store all of the logical addresses and their associated physical positions. The addition of more memory to the array need not increase the time required for the search because each addition of a chip to the array to add more memory adds another controller as well as more memory. In fact, the time for conducting the search may be reduced since searches may be conducted in parallel on the individual chips. The direct on-chip search of the array requires a much smaller general data base which is used essentially for control information and frees area on the flash EEPROM memory array board for memory devices.

Claims

1. A circuit for searching for data patterns in a memory array, the memory array having a plurality of chips of non-volatile memory cells arranged in blocks which are erasable as a group, the blocks of memory cells being adapted to store data in sets each including a logical address identification, the circuit comprising:

a processor for generating commands for controlling the operation of all of the chips;

a command interface on each chip for receiving commands from the processor, for issuing commands to control functions of that chip, and for responding to results of commands issued; and

search logic on each chip, adapted to respond to commands from the command interface, for comparing logical address identification data stored in the blocks of the chip with address data furnished to the command interface and for determining whether the addresses match.

2. A circuit for searching for data patterns in a memory array as claimed in claim 1 wherein the search logic comprises:

a logic circuit for controlling an order of a search;

a circuit which stores a physical address being compared in a block during the search; and

a comparator for comparing logical address identification data to address data furnished for the search.

3. A circuit for searching for data patterns in a memory array as claimed in claim 2 wherein the logical address identification data includes error detection data.

4. A circuit for searching for data patterns in a memory array as claimed in claim 1 wherein the command interface is adapted to respond to commands from the processor to read data stored in a data set for which a search has provided a physical position of the data set.

5. A circuit for searching for data patterns in a memory array as claimed in claim 1 further comprising:

a write state machine, coupled to the command interface for controlling writing of data to blocks of memory devices; and

wherein the command interface is adapted to respond to commands from the processor to write data to an empty portion of the memory array for which a search has provided a physical position of a data set and indicate that the data at the physical position of the data set is invalid.

6. A circuit for searching for data patterns in a memory array as claimed in claim 1 wherein the processor is for generating search commands to all of the plurality of chips simultaneously.

7. A circuit for searching for data patterns in a memory array as claimed in claim 1 in which each of the plurality of chips of non-volatile memory cells comprises a plurality of flash EEPROM memory devices.

8. A computer system comprising:

a central processor;

main memory;

a bus, coupled to the central processor and the main memory, for transferring data; and

a flash EEPROM memory array, coupled to the bus including;

a plurality of chips of flash EEPROM memory devices arranged in blocks which are erasable as a group, and

a circuit for searching for data patterns in the flash EEPROM memory array comprising,

a processor for generating commands for controlling the operation of all of the chips,

a command interface on each chip for receiving commands from the processor, for issuing commands to control functions of that chip, and for responding to results of commands issued, and

a hardware search engine on each chip, adapted to respond to commands from the command interface, for comparing logical address identification data stored in the blocks of the chip with address data furnished to the command interface and for furnishing a physical position of a data set corresponding to the address data to the command interface if the logical address identification data matches the address data.

9. A computer system as claimed in claim 8 wherein the hardware search engine comprises:

a logic circuit for controlling an order of a search;

a circuit which stores a physical address being compared in a block during the search; and

a comparator for comparing logical address identification data stored to address data furnished for the search.

10. A computer system as claimed in claim 9 wherein the logical address identification data includes error detection data for the logical address identification data being compared.

11. A computer system as claimed in claim 8 wherein the command interface is adapted to respond to commands from the processor to read data stored for which a search has provided a physical position of a data set.

12. A computer system as claimed in claim 8 further comprising;

a write state machine, coupled to the command interface, for controlling writing of data to blocks of the memory devices; and

wherein the command interface is adapted to respond to commands from the processor to write data to an empty portion of the memory array for which a search has provided a physical position of a data set and indicated that the data at the physical position of the data set is invalid.

13. A computer system as claimed in claim 8 wherein the processor is capable of generating search commands to all of the plurality of chips simultaneously.

14. A method of searching a memory array, the memory array including a plurality of chips of non-volatile memory devices arranged in blocks, the method comprising the steps of:

(a) initiating a command from a central control for all of the chips, the command including a first logical address for which a physical position is to be retrieved;

(b) transferring the command to a circuit on a first chip of the plurality of chips;

(c) the circuit comparing the first logical address with a plurality of logical addresses stored in blocks on the first chip; and

(d) providing the physical position for the first logical address if the first logical address matches one of the plurality of logical addresses stored in a block on the chip.

15. A method of searching a memory array as claimed in claim 14

wherein the first logical address is stored with an error detecting value;

further comprising a step of generating an error detecting value from the first logical address; and

wherein the comparing step (c) includes comparing both the generated error detecting value and the stored error detecting value.

16. A method of searching a memory array as claimed in claim 14 further comprising a step of returning the physical position for the first logical address to a controller on the chip for initiating an operation with respect to data stored at the physical position.

17. A method of searching a memory array as claimed in claim 16 further comprising a step of initiating a write operation which writes new data to an empty portion of the memory array and invalidates data stored at the physical position.

18. A method of searching a memory array as claimed in claim 16 further comprising a step of initiating a read operation to retrieve data stored at the physical position.

19. A method of searching a memory array as claimed in claim 14 in which the initiating step (a) includes a step of sending the command to each of the plurality of chips simultaneously.

20. A method of searching a memory array as claimed in claim 14 wherein the initiating step (a) includes a step of sending the command to each of the chips serially until the physical position is retrieved or the search fails.

21. A circuit for searching for data patterns in a memory array, the memory array having a plurality of chips of non-volatile memory cells arranged in blocks, the blocks of memory cells being adapted to store data in sets each including a logical address identification, the circuit comprising:

means for generating commands for controlling the operation of the plurality of chips;

means for receiving commands from the means for generating commands;

means for issuing commands to control functions of that chip;

means for responding to results of commands issued;

means for comparing, situated on each chip, logical address identification data stored in the blocks of the chip with address data furnished to the means for receiving; and

means for determining, situated on each chip, whether the addresses match.

22. A circuit for searching for data patterns in a memory array as claimed in claim 21 wherein the means for receiving includes means for responding to commands from the means for generating when read data stored in a data set for which a search has provided a physical position of the data set.

23. A circuit for searching for data patterns in a memory array as claimed in claim 21 wherein the means for generating is for generating search commands to each of the plurality of chips simultaneously.