Multi-port memory emulation using tag registers

• US 5,563,829 A
• Filed: 09/01/1995
• Issued: 10/08/1996
• Est. Priority Date: 03/24/1994
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Huang, Thomas B.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/522,865
• Time in Patent Office: 403 Days
• Field of Search: 365/189.01, 365/230.01, 365/189.02, 365/189.04, 365/189.05, 365/230.02, 365/230.03, 365/230.08
• US Class Current: 365/189.04
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A method of implementing a multi-port memory circuit in the memory resources of configuration logic blocks of programmable logic devices. The multi-port memory circuit to be implemented comprises a memory array having memory locations for storing data, read ports for reading data from the memory array and write ports for writing data to the memory array. Multiple duplications of the memory array are created in order to implement as many read ports and write ports as the multi-port memory circuit being implemented. The memory locations within the duplicate memory arrays are tagged to indicate which memory location had data written therein last so that only the last written data will be read through the various read ports.

Claims

1. A method of implementing a multi-port memory circuit in memory resources of configuration logic blocks of programmable logic devices, the multi-port memory circuit comprising a memory array having X memory locations for storing data, Y read ports for reading data from the memory array and Z write ports for writing data to the memory array, the method comprising the steps of:

creating Z write-port memory arrays, each of said Z write-port memory arrays comprising Y read-port memory arrays, each of said Y read-port memory arrays comprising a duplication of the memory array;

placing each respective of said Y read-port memory arrays of each respective of said Z write-port memory arrays in communication with one of a respective corresponding Y multiplexers; and

tagging the memory location of each of said read-port memory arrays located within one of said Z write-port memory arrays as "last written" when data is written to that memory location.

2. The method of claim 1 wherein said tagging step further includes the steps of:

creating X*Z tag registers, said tag registers having a set input, a reset input and an output; and

placing said output of each of said tag registers in electrical communication with a select input on each of said multiplexers.

3. A method of implementing a multi-port memory circuit in memory resources of configuration logic blocks of programmable logic devices, the multi-port memory circuit comprising a memory array having memory locations for storing data, read ports for reading data from the memory array and write ports for writing data to the memory array, the method comprising the steps of:

duplicating the memory array of the memory circuit being emulated to create a read-port memory array for each read port and thereby creating a write-port memory array;

duplicating said write-port memory array for each of the write ports of the memory circuit being implemented;

placing the output of each respective of the read-port memory arrays in electrical communication with a respective corresponding multiplexer;

tagging the memory location of each of said read-port memory arrays located within one of said write-port memory arrays as "last written" when data is written to that memory location.

4. The method of claim 3 wherein said tagging step further includes the steps of:

creating a tag register for each duplicated memory location located within each write-port memory array, said tag registers having a set input, a reset input and an output; and

placing said output of each of said tag registers in electrical communication with a select input on each of said multiplexers.