Multiport memory and method

• US 5,563,834 A
• Filed: 11/21/1994
• Issued: 10/08/1996
• Est. Priority Date: 08/14/1992
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Young, William R., Longway, Charles W. T.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/345,689
• Time in Patent Office: 687 Days
• Field of Search: 365/203, 365/154, 365/156, 365/233, 365/207, 365/230.05
• US Class Current: 365/203
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.

Claims

1. A method of operating a memory having a clock input and memory cells by cyclically accessing and precharging the memory, the method comprising the steps of:

(a) triggering a memory access phase with a first direction transition of the clock input, the memory access phase comprising a read portion and a write portion, wherein the read portion comprises the step of strobing a sense amplifier coupled to the memory cells, and the write portion commences after the sense amplifier has been strobed;

(b) commencing a memory precharge phase after termination of the memory access phase; and

(c) terminating the memory precharge phase after another first direction transition of the clock input so that the memory precharge phase extends into the next memory access phase.

2. The method of claim 1 wherein further comprising the step of terminating the write portion independent of the clock input.

3. A method of operating a memory in a pipeline memory system having a clock input and memory cells by cyclically accessing and precharging the memory, the method comprising the steps of:

(a) triggering a memory access phase with a first direction transition of the clock input;

(b) commencing a memory precharge phase after termination of the memory access phase;

(c) terminating the memory precharge phase after another first direction transition of the clock input so that the memory precharge phase extends into the next memory access phase; and

(d) providing data output following the another first direction transition until after a next first direction transition of the another first direction transition.

4. The method of claim 3 wherein the step of commencing the memory precharge phase is a function of strobing a sense amplifier coupled to the memory cells.

5. The method of claim 3 wherein the memory access phase comprises a read portion and a write portion, and further comprising the step of self-timing the write portion by the memory, where the timing is independent of the clock input.

6. A method of operating a memory having a clock input and memory cells by cyclically accessing and precharging the memory, the method comprising the steps of:

(a) triggering a memory write phase with a first direction transition of the clock input;

(b) commencing a memory precharge phase after termination of the memory write phase as a function of termination of the memory write phase; and

(c) terminating the memory precharge phase after another first direction transition of the clock input so that the memory precharge phase extends into the next memory write phase.

7. The method of claim 6 further comprising the step of terminating the memory write phase independent of the clock input.

8. The method of claim 7 further comprising the step of self-timing the write portion by the memory.

9. A method of operating a memory having a clock input and memory cells by cyclically accessing and precharging the memory, the method comprising the steps of:

(a) triggering a memory access phase with a first direction transition of the clock input;

(b) commencing a memory precharge phase after termination of the memory access phase as a function of strobing a sense amplifier coupled to the memory cells; and

(c) terminating the memory precharge phase after another first direction transition of the clock input so that the memory precharge phase extends into the next memory access phase.

10. The method of claim 9 operating in a pipeline memory system and further comprising the step of providing data output following the another first direction transition until after a next first direction transition of the another first direction transition.

11. The method of claim 10 operating in a buffered memory system and further comprising the step of providing data output following the start of the strobing of the sense amplifier and continuing the data output until after start of precharging of the sense amplifier in the following memory access phase.

12. The method of claim 9 wherein the memory access phase comprises a read portion and a write portion, and the read portion comprises the step of strobing the sense amplifier, and the write portion commences after the sense amplifier has been strobed.

13. The method of claim 12 further comprising the step of terminating the write portion independent of the clock input.

14. The method of claim 13 further comprising the step of self-timing the write portion by the memory.

15. A memory, comprising:

a clock input;

an array of memory cells arranged in rows and columns;

a sense amplifier coupled to a column of said cells; and

timing circuitry triggered by a first direction transition of said clock input, said timing circuitry for terminating a first precharge of said array and for driving a first precharge of said sense amplifier when triggered by said first direction transition, and after said first precharge of said sense amplifier is complete strobing said sense amplifier, for driving a second precharge of said array until after another said first direction transition at said clock input.

16. The memory of claim 15 in a pipeline memory system and wherein said timing circuitry initiates data output upon a subsequent first direction transition.

17. The memory of claim 15 in a buffered memory system and wherein said timing circuitry initiates data output after said strobing of said sense amplifier and before commencement of said second array precharge.

18. The memory of claim 15 wherein said timing circuitry initiates a write operation after said strobing of said sense amplifier and before said second array precharge.

19. The memory of claim 15 wherein said timing circuitry is not affected by a second direction transition of said clock input that is opposite said first direction transition.

20. The memory of claim 15 wherein said sense amplifier comprises a pair of cross coupled inverters, and a transistor for driving both said inverters, whereby both inverters are driven to equal precharge levels.