Waiting time jitter reduction by synchronizer stuffing threshold modulation

• US 5,563,891 A
• Filed: 09/05/1995
• Issued: 10/08/1996
• Est. Priority Date: 09/05/1995
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wang, Bor-Min
• Primary Examiner(s): Kizou, Hassan
• Application Number:
  US08/524,138
• Time in Patent Office: 399 Days
• Field of Search: 370/102, 370/105.2, 370/105.3, 370/107, 370/112, 375/362, 375/363, 375/371, 375/372, 375/373, 375/376
• US Class Current: 370/505
• CPC Class Codes: H04J 3/073 Bit stuffing, e.g. PDH

Abstract

A system and method are disclosed for reducing waiting time jitter in a pulse-stuffing multiplexer of a communications network. The data of a lower rate signal, that is plesiochronous with a higher rate signal into which the lower rate signal is to be multiplexed, is written into an elastic buffer in accordance with a write signal that is derived from the data of the lower rate signal. The data is read out of the elastic buffer in accordance with a read signal which is locally generated. A comparison circuit forms the phase difference between the write and read signals. A justification circuit generates a justification signal with pulses corresponding to the instances where the phase difference exceeds a dynamically randomly varying threshold. The pulses of the justification signal, in turn, regulate the reading out of the data of the lower rate signal from the elastic buffer.

Claims

1. A process for communicating comprising:

writing a received signal into a buffer in accordance with a write signal derived from said received signal,

reading out said received signal from said buffer in accordance with a locally generated read signal, and

regulating said read signal depending on instances in which a phase difference between said write signal and said read signal exceed a dynamically randomly varying threshold.

2. The process of claim 1 further comprising the steps of:

multiplexing said signal read out of said buffer into a higher rate signal,

demultiplexing said multiplexed signal from said higher rate signal, and

regenerating a smooth clock from said demultiplexed signal using a phase-locked loop.

3. The process of claim 2 wherein said step of regenerating comprises the steps of:

deriving a second write signal from said demultiplexed data,

locally generating a second read signal,

forming a phase difference between said second write signal and said second read signal,

low-pass filtering said phase difference between said second write and said second read signal, and

adjusting the generation of said second read signal depending on said low-pass filtered phase difference signal.

4. The process of claim 3 wherein said step of low-pass filtering further comprises the step of:

filtering out waiting time jitter which was introduced by said step of reading and which was modulated to a higher frequency by said step of regulating.

5. The process of claim 1 wherein said step of regulating modulates low frequency waiting time jitter introduced by said step of reading to a higher frequency.

6. The process of claim 1 wherein said step of regulating further comprises:

forming a phase difference between said write signal and said read signal,

generating a dynamically randomly varying threshold,

comparing said phase difference to said dynamically randomly varying threshold, and

generating a justification signal which comprises a plurality of pulses including one pulse corresponding to each instance in which said phase difference exceeds said dynamically randomly varying threshold.

7. The process of claim 6 further comprising the steps of:

generating a continuous local clock signal,

producing gaps in said continuous local clock signal depending on said pulses of said justification signal, and

enabling the reading out of data from said buffer in said step of reading only in the absence of gaps in said justification signal.

8. The process of claim 6 wherein said dynamically randomly varying threshold is a repeating sequence of pseudo random values.

9. The process of claim 8 further comprising the step of:

preliminarily generating an optimum sequence of pseudo random values, and

generating said dynamically randomly varying threshold by reading out said optimum sequence of pseudo random values.

10. The process of claim 1 further comprising:

multiplexing said signal read out during said step of reading out into payload and stuffing bit positions of a channel corresponding to said received signal.

11. The process of claim 10 wherein said stuffing bits contain data of said read out signal or a null bit depending on a relative rate of said write signal and said read signal.

12. The process of claim 1 wherein said write signal is a write pointer signal derived by incrementing a write pointer with each clock pulse of a write clock generated from said received signal.

13. The process of claim 1 wherein said read signal is a read pointer signal generated by incrementing a read pointer with each clock pulse of a locally generated clock.

14. A process for multiplexing plural plesiochronous signals into respective time slots of a higher rate signal comprising the steps of:

for each lower rate signal;

writing data of said lower rate signal into a buffer in accordance with a write signal derived from said data of said lower rate signal,

reading out said data of said lower rate signal from said buffer in accordance with a locally generated read signal, and

regulating said read signal depending on instances in which a phase difference between said write signal and said read signal exceed a dynamically randomly varying threshold, and

multiplexing said data of each lower rate signal read out during said step of reading out into a respective time slot of said higher rate signal.

15. The process of claim 14 further comprising:

demultiplexing said data of each lower rate signal, and for said data of each lower rate signal;

writing data of said lower rate signal into a second buffer in accordance with a second write signal derived from said higher rate signal,

generating a smooth second read signal from said second write signal using a phase locked loop, and

reading out said data of said lower rate signal from said second buffer in accordance with said second read signal.

16. A synchronizer for synchronizing a received plesiochronous signal comprising:

a buffer, in which said received signal is written in accordance with a write signal that is derived from said received signal, and from which said received signal is read out in accordance with a locally generated read signal, and

a justification decision circuit receiving a dynamically randomly varying threshold and a phase difference between said write signal and said read signal for regulating said reading out of said local signal from said buffer depending on instances in which said phase difference exceeds said dynamically randomly varying threshold.

17. The synchronizer of claim 16 further comprising:

a memory for storing a sequence of pseudo random threshold values and for outputting said sequence of pseudo random threshold values to said justification decision circuit as said dynamically randomly varying threshold.

18. The synchronizer of claim 16 further comprising:

a write clock recovery circuit, for recovering a write clock from said received signal and outputting said write clock to a write clock input of said buffer,

a write counter, receiving said write clock, for incrementing a write pointer therein, and for outputting said write pointer to a write address input of said buffer,

a logic circuit for receiving a justification signal from said justification circuit and said read clock signal and for outputting a gapped read clock in response thereto to a read clock input of said buffer, and

a read counter, for receiving said gapped read clock, for incrementing a read pointer therein, and for outputting said read pointer to a read address input of said buffer.

19. A communication system comprising

a synchronizer for multiplexing plural received plesiochronous signals into respective time slots of a higher rate signal comprising:

for each received signal;

a buffer, in which said received signal is written in accordance with a write signal that is derived from said received signal, and from which said received signal is read out in accordance with a locally generated read signal, and

a justification decision circuit receiving a dynamically randomly varying threshold and a phase difference between said write signal and said read signal for regulating said reading out of said received signal from said buffer depending on instances in which said phase difference exceeds said dynamically randomly varying threshold, and

a multiplexer for multiplexing each received signal read out of said buffer into a respective time slot of said higher rate signal.

20. The communication system of claim 19 further comprising:

a demultiplexer for demultiplexing each multiplexed signal from said higher rate signal, and, for each demultiplexed signal;

a buffer, in which said demultiplexed signal is written in accordance with a second write signal that is derived from said higher rate signal, and from which said demultiplexed signal is read out in accordance with a second locally generated read signal, and

a phase-locked loop receiving said second write signal and generating said second read signal therefrom.