CPU activity monitoring through cache watching

• US 5,564,015 A
• Filed: 12/28/1995
• Issued: 10/08/1996
• Est. Priority Date: 05/12/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: AST Research, Inc. (Samsung Electronics Co. Ltd.)
• Inventors: Bunnell, James C.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Decady, Albert
• Application Number:
  US08/581,305
• Time in Patent Office: 285 Days
• Field of Search: 395/184.01, 395/459, 395/838, 395/750, 364/270, 364/273.1, 364/707
• US Class Current: 714/47.2
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 11/3423 where the assessed time is active or idle time
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A central processing unit ("CPU") activity monitor and method provides CPU activity information. The CPU activity monitor includes a timer and an activity event counter for receiving a plurality of mode signals from the CPU, a cache miss signal from a cache memory system, and a clock signal from a clock. An activity-to-inactivity value defines when the CPU transitions from an active state to an inactive state. An activity threshold defines when the CPU transitions from an inactive state to an active state.

Claims

1. A processing unit activity monitoring device comprising:

a timer in communication with a clock, said timer providing a time signal that indicates an end of a time interval;

a stack information signal which indicates when a processor accesses a stack;

a counter in communication with said processor and a cache memory unit, said counter receiving a cache miss signal and said processor stack information signal wherein said cache miss signal and said stack information signal determine an occurrence of an activity event, said counter counting each activity event to provide a count; and

a comparator in communication with said time signal and said counter, said comparator further receiving an activity threshold value, wherein said comparator compares said count provided by said counter with said activity threshold value during said time interval to provide an event signal that indicates the magnitude of said count with respect to said activity threshold.

2. The processor activity monitoring device as defined in claim 1, further comprising a first storage location for storing an activity-to-inactivity transition value.

3. The processor activity monitoring device as defined in claim 2, further comprising a second storage location for storing an inactivity-to-activity threshold.

4. A central processing unit ("CPU") activity monitoring device comprising:

a timer in communication with a clock, said timer providing a time signal that indicates an end of a time interval;

a counter in communication with a CPU and a cache memory unit, said counter receiving a cache miss signal and a CPU stack information signal which indicates when said CPU accesses a stack, wherein said cache miss signal and said CPU stack information signal determine an occurrence of an activity event, said counter counting each activity event to provide a count;

a storage location for storing an activity-to-inactivity transition value; and

a comparator in communication with said time signal, said counter, and said storage location, wherein said comparator compares said count with said activity-to-inactivity transition value during said time interval to provide an activity event flag that indicates a transition by said CPU from an inactive state to an active state.

5. The CPU activity monitoring device as defined in claim 4, wherein said activity-to-inactivity transition value specifies a maximum number of activity events that may occur within said time interval.

6. The CPU activity monitoring device as defined in claim 5, wherein said activity events are data write and data read cycles to main memory that generate a cache miss signal.

7. The CPU activity monitoring device as defined in claim 5, wherein said activity events are data write cycles to main memory that generate a cache miss signal.

8. The CPU activity monitoring device as defined in claim 7, further comprising:

an inactivity event flag in communication with said comparator, said comparator asserting said inactivity event flag in response to a transition by said CPU from said active state to said inactive state.

9. The CPU monitoring system as defined in claim 8, further comprising an interrupt request signal in communication with said activity event flag and said inactivity event flag, said interrupt request signal responsive to the assertion of said activity event flag or said inactivity event flag.

10. A CPU activity monitoring device comprising:

a timer in communication with a clock, said timer providing a time signal that indicates an end of a time interval;

a counter in communication with a CPU and a cache memory unit, said counter receiving a cache miss signal and a plurality of CPU mode signals wherein said cache miss signal and said plurality of CPU mode signals determine an occurrence of an activity event, said counter counting each activity event to provide a count;

a first storage location for storing an activity-to-inactivity transition value said activity-to-inactivity transition value defining the number of activity events which signal when said CPU transitions from an active state to an inactive state;

an inactivity comparator coupled to said timer, said counter, and said first storage location, wherein said inactivity comparator compares said activity-to-inactivity transition value with said count of said activity events to provide an inactivity event flag;

a second storage location for storing an activity threshold, said activity threshold defining the number of successive time intervals in which the number of said activity events rise above the activity-to-inactivity transition value; and

an activity comparator in communication with said time signal, said counter, and said second storage location, wherein said activity comparator compares said count of said successive time intervals with said activity threshold to provide an activity event flag.

11. The CPU activity monitoring device as defined in claim 10, wherein said activity-to-inactivity transition value specifies the maximum number of activity events that may occur within said time interval.

12. The CPU activity monitoring device as defined in claim 10, further comprising an interrupt request signal in communication with said inactivity event flag and said activity event flag, said interrupt requests signal responsive to an assertion of said inactivity event flag or an assertion of said activity event flag.

13. The CPU activity monitoring device as defined in claim 10, wherein said activity events are data write cycles to main memory that generate a cache miss signal.

14. A method for monitoring processor activity comprising the steps of:

defining a time interval;

generating a cache miss signal;

generating a a stack information signal which communicates when a processor accesses a stack;

monitoring said stack information signal and said cache miss signal to determine an activity event;

counting each activity event; and

putting said processor into an active or an inactive state in accordance with said count of said activity events that occur within said time interval.

15. A method for monitoring processor activity comprising the steps of:

defining a time interval;

generating a clock signal;

monitoring said clock signal to determine an end of said time interval;

generating a stack information signal which communicates when a processor accesses a stack;

generating a cache miss signal when data is not stored in a cache memory system;

monitoring said plurality of mode signals and said stack information signal to determine an activity event;

counting each activity event that occurs within said time interval;

defining an activity transition value which corresponds to a minimum number of said activity events that an active processor generates within said time interval; and

generating an event signal when said processor transitions from an active state to said inactive state, or when said processor transitions from said inactive state to said active state.

16. The method as defined in claim 15, wherein said activity event is a data write cycle or a data read cycle that generates a cache miss signal.

17. The method as defined in claim 15, wherein said activity event is a data write cycle that generates a cache miss signal.

18. A method for monitoring CPU activity comprising the steps of:

defining a time interval;

generating a clock signal;

monitoring said clock signal to determine the expiration of said time interval;

generating a plurality of mode signals that correspond to the operating mode of a central processing unit;

generating a cache miss signal when data is not stored in a cache memory system; and

monitoring said plurality of mode signals and said cache miss signal to determine an activity event;

counting each activity event that occurs within said time interval;

defining an activity-to-inactivity transition value which specifies the maximum number of said activity events occurring within said time interval when said CPU transitions from an active state to an inactive state;

generating an inactivity event signal when said time interval expires before said count of said activity events is greater than said activity-to-inactivity transition value;

defining an activity threshold value which Specifies the number of successive time intervals in which the number of CPU activity events rise above the activity-to-inactivity transition value; and

generating an activity event signal when said count of said activity events occurring within said successive time intervals is equal to or greater than said activity threshold.

19. The method as defined in claim 18, wherein said activity event is a data write cycle or a data read cycle that generates a cache miss signal.

20. The method as defined in claim 18, wherein said activity event is a data write cycle that generates a cache miss signal.