Method and apparatus for automatically inserting clock buffers into a logic block to reduce clock skew

• US 5,564,022 A
• Filed: 02/09/1994
• Issued: 10/08/1996
• Est. Priority Date: 02/09/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Debnath, Goutam, Fitzpatrick, Kelly J.
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US08/193,789
• Time in Patent Office: 972 Days
• Field of Search: 395/250, 395/550, 326/38, 326/85, 327/158, 327/141, 364/491
• US Class Current: 713/503
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method and apparatus for inserting clock buffers to reduce clock skew in a logic block in which the proper placement of the cells within the logic block is first determined. Given this cell placement and the location of the local clock lines, the placement of clock buffers within the logic block is determined such that the clock buffers are in close proximity to the local clock lines. Routing is then performed to connect the clock buffers to their corresponding clock trunks and the cells requiring clock signals to their corresponding clock buffers. The performance of the logic block is then evaluated. If the performance does not satisfy a predetermined minimum threshold then the cells are modified to satisfy the minimum threshold, or come closer to attaining it. The clock buffers are removed, and the proper placement of the new cells within the logic block is determined. Given this new cell placement a new set of clock buffers is placed and a new routing is created. The performance is then re-evaluated and, if the minimum threshold still has not been attained, the above process is repeated.

Claims

1. A method for automatically reducing clock skew in a logic block having a plurality of cells, the method comprising the steps of:

(a) determining a placement of said plurality of cells within said logic block;

(b) determining a placement of a plurality of clock buffers within said logic block such that each clock buffer of said plurality of clock buffers is located in close proximity to a clock line; and

(c) determining a routing between said plurality of clock buffers, said plurality of cells and said clock line.

2. A method for reducing clock skew as claimed in claim 1 further comprising the step of:

(d) determining the performance of said logic block.

3. A method for reducing clock skew as claimed in claim 2 further comprising the steps of:

(e) removing said plurality of clock buffers from said logic block if said performance is below a predetermined minimum threshold;

(f) modifying at least one cell of said plurality of cells if said performance is below said minimum threshold; and

(g) repeating steps (a) through (g) if said performance is below said minimum threshold.

4. A method for reducing clock skew as claimed in claim 1 wherein said step of determining a placement of a plurality of clock buffers comprises locating each clock buffer of said plurality of clock buffers in a closest available position to a clock line.

5. A method for reducing clock skew as claimed in claim 1 wherein said step of determining a placement of said plurality of cells comprises receiving a description of connectivity between a plurality of cells.

6. A method for reducing clock skew as claimed in claim 1 wherein said step of determining a placement of a plurality of clock buffers further comprises receiving a description of the location of said clock line.

7. A method for reducing clock skew as claimed in claim 1 wherein said step of determining a placement of said plurality of cells comprises placing said cells within a plurality of rows.

8. A method for reducing clock skew as claimed in claim 1 wherein said step of determining the placement of a plurality of clock buffers further comprises placing a first set of clock buffers of a first clock buffer type corresponding to a first clock and placing a second set of clock buffers of a second clock buffer type corresponding to a second clock.

9. A method for reducing clock skew as claimed in claim 1 wherein said step of determining the placement of said plurality of clock buffers further comprises placing a first set of clock buffers corresponding to a first clock line and placing a second clock buffer corresponding to a second clock line.

10. A method for reducing clock skew as claimed in claim 1 wherein said step of determining said routing comprises coupling each buffer of said plurality of buffers to said clock line and coupling each cell of said plurality of cells requiring a clock signal to a buffer of said plurality of buffers such that no cell requiring a clock signal is directly coupled to said clock line.

11. A method for automatically inserting buffers into a logic block having a plurality of cells, the method comprising the steps of:

(a) determining a placement of a plurality of cells within said logic block;

(b) determining a placement of a plurality of buffers within said logic block;

(c) determining a routing between said plurality of buffers, said plurality of cells and said clock line;

(d) determining the performance of said logic block;

(e) removing said plurality of buffers from said logic block if said performance is below a predetermined minimum threshold;

(f) modifying a cell of said plurality of cells if said performance is below said minimum threshold; and

(g) repeating steps (a) through (g) if said performance is below said minimum threshold.

12. The method of claim 11 wherein said step (b) comprises determining a placement of a plurality of buffers within said logic block such that each clock buffer of said plurality of buffers is located in close proximity to a clock line.

13. The method of claim 11 wherein said step (b) comprises locating each buffer of said plurality of buffers in the closest available position to a clock line.

14. The method of claim 11 wherein said step (a) comprises placing said cells within a plurality of rows.

15. The method of claim 11 wherein said step (b) comprises placing a first buffer of a first buffer type and placing a second buffer of a second buffer type.

16. The method of claim 11 wherein said step (b) comprises placing a first buffer corresponding to a first clock line and placing a second clock buffer corresponding to a second clock line.

17. The method of claim 11 wherein said step (c) comprises coupling each buffer of said plurality of buffers to said clock line and coupling each cell of said plurality of cells requiring a clock signal to a buffer of said plurality of buffers such that no cell requiring a clock signal is directly coupled to said clock line.

18. The method of claim 11 wherein said step (g) comprises determining a placement of a buffer and repeating steps (c) through (g).

19. An apparatus for inserting clock buffers into a logic block having a plurality of cells to reduce clock skew, the apparatus comprising:

a bus;

a memory device which stores a set of available clock buffers, wherein the memory device is coupled to the bus; and

a processor, coupled to the bus, for

determining a placement of a plurality of cells within said logic block,

determining a placement of a plurality of clock buffers selected from the set of available clock buffers within said logic block such that each clock buffer of said plurality of clock buffers is located in close proximity to a clock line,

determining the routing between said plurality of clock buffers, said plurality of cells and said clock line,

determining the performance of said logic block,

removing said plurality of clock buffers from said logic block if said performance is below a predetermined minimum threshold, and

modifying a cell of said plurality of cells if said performance is below said minimum threshold.

20. An apparatus for inserting clock buffers as claimed in claim 19 wherein said processor for determining a placement of a plurality of clock buffers is also for locating each clock buffer of said plurality of clock buffers in a closest available position to a clock line.

21. An apparatus for inserting clock buffers as claimed in claim 19 wherein said processor for determining the placement of said plurality of cells places said cells within a plurality of rows.

22. An apparatus for inserting clock buffers as claimed in claim 19 wherein said processor for determining the placement of said plurality of clock buffers is also for placing a first set of clock buffers of a first clock buffer type corresponding to a first clock and placing a second set of clock buffers of a second clock buffer type corresponding to a second clock.

23. An apparatus for inserting clock buffers as claimed in claim 19 wherein said processor for determining the placement of said plurality of clock buffers is also for placing a first set of clock buffers corresponding to a first clock line and placing a second clock buffer corresponding to a second clock line.

24. An apparatus for inserting clock buffers as claimed in claim 19 wherein said processor for determining said routing is also for coupling each buffer of said plurality of buffers to said clock line and coupling each cell of said plurality of cells which requires a clock signal to a buffer of said plurality of buffers such that no cell requiring a clock signal is directly coupled to said clock line.