Ultra low-power integrated circuit for pseudo-baseband down-conversion of GPS RF signals

• US 5,564,098 A
• Filed: 09/13/1994
• Issued: 10/08/1996
• Est. Priority Date: 09/13/1994
• Status: Expired due to Fees

• Current Assignee: Trimble Navigation Limited (Trimble Inc.)
• Original Assignee: Trimble Navigation Limited (Trimble Inc.)
• Inventors: Rodal, Eric B., Wagner, Gary L., Lau, Chung Y.
• Primary Examiner(s): Faile, Andrew
• Assistant Examiner(s): Nguyen, Tri
• Application Number:
  US08/305,356
• Time in Patent Office: 756 Days
• Field of Search: 455/302, 455/303, 455/207, 455/209, 455/323, 455/313, 455/314, 455/315, 455/316, 455/317, 455/318, 455/319, 375/261
• US Class Current: 455/314
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: H03D 7/16 Multiple-frequency-changing
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16

Abstract

A GPS receiver downconverter combines on a single integrated circuit, a first super-heterodyne mixer, a voltage controlled oscillator, a phase locked loop, a pair of quadrature mixers and a pair of quantizers with in-phase and quadrature-phase sampler outputs operable at twenty-five MHz and 2.5 MHz. Emitter-coupled logic and special low-voltage bipolar semiconductor technology are combined for 3.3 volt operation at under one hundred milliwatts.

Claims

1. A radio frequency down-conversion integrated circuit (IC) for use in a satellite navigation receiver to amplify L-band microwave radio transmissions received from orbiting satellites and to downconvert such signals to a pseudo-baseband signal for sampling, comprising:

a low-voltage bipolar-process emitter-coupled-logic (ECL) single semiconductor chip (10);

a radio frequency (RF) pre-amplifier (11) disposed in the IC 10 and connected to amplify signals from an L-band microwave signal input (74);

a first mixer (12) disposed in the IC (10) and connected to a first output (32) from a local oscillator frequency synthesizer section (32-54) and the RF preamplifier (11) for down-conversion of signals from said L-band microwave signal input (74) to approximately 175 MHz;

an intermediate frequency (IF) amplifier (14) disposed in the IC (10) and connected to the first mixer (12) and having an external off-chip bandpass filter connection (16);

an IF amplifier (18) disposed in the IC (10) and connected to said external off-chip bandpass filter connection (16);

an in-phase (I) quadrature mixer (20) disposed in the IC (10) and connected to the IF amplifier (18) and a second output (40) from said local oscillator frequency synthesizer section (32-54);

a pseudo-baseband amplifier (22) disposed in the IC (10) and connected to amplify signals from the in-phase (I) quadrature mixer (20) to an external off-chip baseband filter connection (24);

a pseudo-baseband amplifier (26) connected to an I-sample/amplifier stage (28) and a quantizer (30) and all disposed in the IC (10) and connected to a control line (68) that provides for an external selection of whether said I-sample/amplifier stage (28) is to operate as a sampler or as an amplifier, wherein when operated as a sampler, the overall power consumption of the IC (10) is reduced, as the high-frequency, power-consuming signals driven out by quantizer (30) is eliminated and can change only at a sample clock rate;

a quadrature-phase (Q) quadrature mixer (56) disposed in the IC (10) and connected to the IF amplifier (18) and a third output (42) from said local oscillator frequency synthesizer section (32-54);

a pseudo-baseband amplifier (58) connected to an external off-chip baseband filter connection (60); and

a pseudo-baseband amplifier (62) connected to a Q-sample/amplifier stage (64) and a quantizer (66) and all disposed in the IC (10) and connected to said control line (68) that further provides for an external selection of whether said Q-sample/amplifier stage (64) is to operate as a sampler or as an amplifier, wherein when operated as a sampler, the overall power consumption of the IC (10) is reduced, as the high-frequency, power-consuming signals driven out by quantizer (66) is eliminated and can change only at said sample clock rate.

2. The IC of claim 1, wherein:

said local oscillator frequency synthesizer section (32-54) comprises a local oscillator (LO) amplifier (32), a voltage-controlled oscillator (VCO) (34), an amplifier (36), a set of three cascaded flip-flops (38, 40 and

     42) arranged in a divide-by-eight, a low-pass integrating amplifier (44) with an external off-chip compensation connection (46), an external off-chip resonator connection (48), a phase detector (50), a reference frequency amplifier (52), and a divide by fourteen counter (54).

3. The IC of claim 1, wherein:

the radio frequency (RF) pre-amplifier (11) amplifies a separate first and second pair of microwave radio carriers that are nominally 1575.42 MHz and 1227.6 MHz;

said first output (32) from said local oscillator frequency synthesizer section (32-54) provides a first frequency synthesizer beat frequency of approximately 1400 MHz;

said second output (40) from said local oscillator frequency synthesizer section (32-54) provides a second frequency synthesizer beat frequency of approximately 175 MHz and one-eighth of said first beat frequency;

said third output (42) from said local oscillator frequency synthesizer section (32-54) provides a third frequency synthesizer beat frequency of approximately 175 MHz in quadrature to said second frequency synthesizer beat frequency and one-eighth of said first beat frequency; and

the pseudo-baseband amplifiers (22,

     58) provide baseband signals that are nominally centered at 420 KHz and 2.6 MHz, respectively for said first and second pair of microwave radio carriers.

4. The IC of claim 1, wherein:

said I-sample/amplifier stage (28) and said Q-sample/amplifier stage (64) are connected to receive sampling clocks of approximately twenty-five MHz for a normal mode and 2.5 MHz for a low-power mode operation.

5. The IC of claim 1, wherein:

said local oscillator frequency synthesizer section (32-54) comprises a voltage controlled oscillator (34) operated at approximately 1400 MHz with an external off-chip resonator (48) and connected to a phase detector (50) and digital divider (38, 40,

     42) in a phase-locked loop configuration and a connection (72) on said phase detector (50) to receive (52) an external 12.5 MHz reference frequency.