Method and an arrangement for handshaking on a bus to transfer information between devices in a computer system

• US 5,564,114 A
• Filed: 01/09/1995
• Issued: 10/08/1996
• Est. Priority Date: 01/09/1995
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Sugie, Fukuji, Popat, Kaushik L.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Travis, John
• Application Number:
  US08/369,968
• Time in Patent Office: 638 Days
• Field of Search: 395/285, 395/290, 395/280
• US Class Current: 710/105
• CPC Class Codes: G06F 13/4226 with asynchronous protocol

Abstract

A computer system is provided with a central processing unit (CPU), a bus master coupled to the CPU, and a plurality of interface cards that interface the computer system with peripheral devices. A plurality of host adapters are coupled between the bus master and the interface cards. The host adapters adapt signals between the CPU and the interface cards. Each host adapter generates a ready signal that when asserted indicates readiness of the host adapter to receive address information from the bus master and have data information read by the bus master. An address/data bus is coupled between the bus master and the host adapters. A single separate ready line is coupled between each of the host adapters and the bus master, each ready line carrying the ready signal from a different one of the host adapters to the bus master. The single ready signal carried by a single line serves both an address ready and a data ready signalling function, to thereby, reduce the pin count in the host adapter serving as a slave.

Claims

1. A computer system comprising:

a central processing unit (CPU);

a master coupled to the CPU;

a plurality of interface cards that interface the computer system with peripheral devices;

a plurality of host adapters coupled between the master and the interface cards, the host adapters adapting signals between the CPU and the interface cards, each host adapter generating a ready signal that when asserted indicates at least one of readiness of the host adapter to receive address information from the master and to have data information read by the master;

an address/data bus coupled between the master and the host adapters;

plurality of ready lines, each coupled between a corresponding one of the host adapters and the master, each ready line carrying the ready signal from the corresponding host adapter to the master.

2. The computer system of claim 1, further comprising a shared chip enable line coupled between the master and the host adapters, the master generating a chip enable signal that, when asserted, enables all of the host adapters for receiving address information and receiving or transferring data information.

3. The computer system of claim 2, wherein the master includes means for asserting the address information on the address/data bus to initiate a transfer with one of the host adapters, the address information containing a host adapter identifier that identifies a transfer host adapter, which is the host adapter with which the master is to perform the transfer.

4. The computer system of claim 3, wherein each host adapter includes means for recognizing the host adapter identifier, means for deasserting the ready signal after recognizing the host adapter identifier to indicate that the host adapter is not ready to have data information read by the master;

and means for reasserting the ready signal when the host adapter is ready to have the data information read by the master.

5. The computer system of claim 4, wherein the master includes means for sampling the ready line of the transfer host adapter at a first defined time after the address information has been asserted, and means for deasserting the chip enable signal when the means for sampling determines that the ready signal of the transfer host adapter is deasserted.

6. The computer system of claim 5, wherein the master includes means for resampling the ready line of the transfer host adapter a second defined time after the chip enable signal is deasserted by the means for deasserting the chip enable signal.

7. The computer system of claim 6, wherein the master includes means for asserting the data information in a write operation directly after the address information on the address/data bus.

8. The computer system of claim 7, wherein the master includes means for reading in a read operation the data information from the transfer host adapter when the means for sampling or the means for resampling determines that the ready signal of the transfer host adapter is asserted and the chip enable signal is asserted.

9. The computer system of claim 8, wherein the first defined time is one cycle.

10. The computer system of claim 9, wherein each host adapter includes means for pulsing its ready signal in response to recognition of the host adapter identifier by the means for recognizing the host adapter identifier to confirm to the master that the host adapter has recognized the host adapter identifier.

11. The computer system of claim 10, wherein the interface card is a personal computer memory card international association (PCMCIA) card.

12. A host adapter for adapting signals between an input/output (I/O) device interface and a computer system, comprising:

means for adapting address and data signals between the I/O device interface and the computer system; and

means for producing a single ready signal that indicates readiness of the host adapter to receive address information and to have data information read.

13. The host adapter of claim 12, further comprising means for recognizing a host adapter identifier that identifies a host adapter with which the computer system is to perform a transfer.

14. The host adapter of claim 13, further comprising means for deasserting the ready signal after recognizing the host adapter identifier to indicate that the host adapter is not ready to transmit data information from or to the bus master;

and means for reasserting the ready signal when the host adapter is ready to have data information read by the bus master.

15. The host adapter of claim 13, further comprising means for pulsing its ready signal in response to recognition of the host adapter identifier by the means for recognizing the host adapter identifier to confirm that the host adapter has recognized the host adapter identifier.

16. The host adapter of claim 14, wherein the host adapter is a personal computer memory card international association (PCMCIA) adapter.

23. The host adapter of claim 12, wherein the adapting means adapts said address and data signals between an address/data bus coupled to the computer system and the I/O device interface, the single ready signal indicating at least one of readiness of the host adapter to receive said address information from the address/data bus and readiness to have said data information read for transmission on the address/data bus.

17. A method of transferring information between a master and a slave, the method comprising:

producing a single ready signal at the slave that indicates at least one of readiness of the slave to receive address information and readiness of the slave to have data information read; and

sending the address information to the slave from the master to initiate a transfer when the ready signal indicates that the slave is ready to receive the address information; and

subsequently reading the data information from the slave by the master when the ready signal indicates that data information is ready to be read from the slave by the master.

18. The method of claim 17, further comprising sampling the ready signal after a predefined time following the sending of the address information to ascertain whether the data information is ready to be read.

19. The method of claim 17, further comprising deasserting a chip enable signal when the sampling of the ready signal indicates that the data information is not ready to be read.

20. The method of claim 19, further comprising resampling the ready signal following the deassertion of the chip enable signal and reasserting the chip enable signal in response to the ready signal indicating that the data information is ready to be read from the slave by the master, the master subsequently reading the data information.

21. The method of claim 17, further comprising writing the data information to the slave from the master immediately following the sending of the address information to the slave.

22. The method of claim 17, further comprising decoding the address information by the slave to determine if the slave is to participate in the transfer.

24. The method of claim 17, wherein:

the sending step comprises sending the address information to the slave from the master via an address/data bus; and

said reading step comprises the step of reading the data information from the slave by the master via the address/data bus.