Neural network architecture with connection pointers

• US 5,564,115 A
• Filed: 02/18/1994
• Issued: 10/08/1996
• Est. Priority Date: 06/21/1991
• Status: Expired due to Fees

• Current Assignee: King's College London
• Original Assignee: King's College London, University College London (University of London)
• Inventors: Clarkson, Trevor G.
• Primary Examiner(s): Davis, George B.
• Application Number:
  US08/167,883
• Time in Patent Office: 963 Days
• Field of Search: 395/27, 395/22, 395/20
• US Class Current: 706/28
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A neural network unit is described which has a plurality of neurons. The network comprises a RAM, which provides a plurality of storage locations for each of the neurons and an integrated circuit. The integrated circuit including means for defining an algorithm for the operation of the neurons and a control unit for causing the neurons to produce outputs on the basis of data stored in the storage locations and the algorithm. The integrated circuit may have a random number generator and a comparator. In effect, the neurons are virtual pRAMs (probabilistic RAMs).

Claims

1. A neural network comprising a first module and a plurality of further modules, each respective one of the further modules being connected directly to the first module by a connection whose ends are at the first module and the respective further module, each of the modules having a plurality of neurons, and each of the modules comprising a memory providing a plurality of storage locations for each of the neurons, and, in an integrated circuit, means for defining an algorithm for operation of the neurons and a control unit for causing the neurons to produce outputs on the basis of data stored in the storage locations and the algorithm, each of the modules further comprising a connection pointers table defining which neuron outputs or external inputs are connected to which neuron inputs.

2. A network according to claim 1, wherein, in each module, the integrated circuit is distinct from the memory.

3. A network according to claim 1, wherein in each module, the integrated circuit further defines a learning algorithm by means of which the neurons can undergo a learning process.

4. A network according to claim 1, wherein each module comprises an output list which holds current outputs of the neurons of the module, and a further output list which holds previous outputs of the neurons of the module and the previous outputs of the neurons of the other modules to which it is connected.

5. A network according to claim 4, wherein the output lists are held in the memory.

6. A network according to claim 4, wherein the output lists are held in the integrated circuit.

7. A network according to claim 1, wherein, in each module, the connection pointers table is held in the memory.

8. A network according to claim 1, wherein, in each module, the connection pointers table is held in the integrated circuit.

9. A network according to claim 1, wherein, in each module, the means defining the neuron algorithm comprises a random number generator and a comparator for comparing the contents of the storage locations with random numbers produced by the random number generator, the comparator having an output at which appears a signal having a first or second value depending on the result of the comparison, the comparator outputs constituting the neuron outputs.