IC protection structure having n-channel MOSFET with n-type resistor region

• US 5,565,698 A
• Filed: 07/06/1995
• Issued: 10/15/1996
• Est. Priority Date: 07/06/1994
• Status: Expired due to Fees

• Current Assignee: Deutsche ITT Industries GmbH (TDK Corporation)
• Original Assignee: Deutsche ITT Industries GmbH (TDK Corporation)
• Inventors: Obermeier, Cornelius
• Primary Examiner(s): Limanek, Robert P.
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/498,822
• Time in Patent Office: 467 Days
• Field of Search: 257/355, 257/565, 257/357, 257/356, 257/358, 257/360, 257/363, 257/364, 257/536
• US Class Current: 257/360
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A protection structure for integrated circuits with an n-channel MOS field-effect transistor has a more stable bipolar state, with the change to the bipolar state occurring fast. Below the drain region and the drain contact region an n-type resistor region doped more lightly than the drain region and the drain contact region is formed to provide the electrically conductive connection between the drain region and the drain contact region. When a positive voltage pulse is applied to the drain contact region, the n-channel MOS transistor will go into a bipolar operating state upon reaching the drain-source or drain-substrate breakdown voltage. The conductor paths are typically connected to ground. The n-well forms a series resistor between the drain region and the drain contact region of the respective transistor. It also forms a pn junction between the drain region and the channel, the collector pn junction, which extends deep into the substrate. Because of the series resistance of this n-well, during the change to the bipolar state, contractions of the current occurring at the pn junction are prevented. In the bipolar state, the transistor can absorb more power than with conventional arrangements. By connecting two or more transistors in parallel, the current is distributed even further, so that the power can be absorbed by both transistors, since the dissipation is distributed over an even larger area.

Claims

1. An improved protection structure for an integrated circuit having an input element, comprising:

a semiconductor body having a top surface;

an n-channel transistor on said semiconductor body, said n-channel transistor having a drain region for coupling said protection structure to the input element of the integrated circuit, a drain contact region, a source region, and a gate region;

an n-type resistor region positioned below said drain region and said drain contact region, said n-type resistor region more lightly doped than said drain region and said drain contact region;

wherein said drain region and said drain contact region are coupled by said n-type resistor region, whereby said structure protects the integrated circuit against electrostatic discharge overloading.

2. The device as recited in claim 1, wherein said n-type resistor region extends laterally below said top surface and terminates before said gate region.

3. The device as recited in claim 1, wherein said n-type resistor region extends below all of said drain contact region.

4. The device as recited in claim 1 further comprising:

an insulating layer on said top surface of said semiconductor body, said insulating layer positioned between said drain region and said drain contact region.

5. The device as recited in claim 1, wherein said n-type resistor region is at least 10 μ

m wide.

6. The device as recited in claim 1, wherein said n-type resistor region is generally 100 μ

m wide.

7. The device as recited in claim 1, wherein said n-type resistor region has a depth 3 to 5 times a depth of said drain region and a depth of said drain contact region.

8. The device as recited in claim 1 further comprising:

an n-type source resistor region positioned below said source region, said n-type source resistor region more lightly doped than said source region.

9. The device as recited in claim 8, wherein said n-type source resistor region is at least 10 μ

m.

10. The device as recited in claim 8, wherein said n-type source resistor region is generally 100 μ

m.

11. The device as recited in claim 8, wherein said n-type source resistor region has a depth 3 to 5 times a depth of said source region.

12. The device as recited in claim 1, wherein said n-channel transistor is an n-channel MOSFET.

13. An improved protection structure for an integrated circuit having an input element, comprising:

an n-channel MOS field-effect transistor, wherein below a drain region for coupling said protection structure to the input element of the integrated circuit and a drain contact region, an n-type resistor region doped more lightly than the drain region and the drain contact region is formed to provide an electrically conductive connection between the drain region and the drain contact region, whereby said structure protects the integrated circuit against electrostatic discharge overloading.

14. The device as recited in claim 13, wherein the n-type resistor region extends laterally below said top surface and terminates before an interface where said gate region and said gate region meet.

15. The device as recited in claim 13, wherein the n-type resistor region extends below the entire drain contact region.

16. The device as recited in claim 13, wherein the drain region and the drain contact region are separated by an insulating layer located at a semiconductor surface.

17. The device as recited in claim 13, wherein the n-type resistor region is more than 10 μ

m wide.

18. The device as recited in claim 13, wherein the n-type resistor region is generally 100 μ

m wide.

19. The device as recited in claim 13, wherein the n-type resistor region has a depth that is 3 to 5 times greater than a depth of the drain region and the drain contact region.

20. The device as recited in claim 13, wherein below the source region an n-type region doped more lightly than the source region is provided.