Semiconductor circuit element device with arrangement for testing the device and method of test

• US 5,565,766 A
• Filed: 09/28/1992
• Issued: 10/15/1996
• Est. Priority Date: 09/30/1991
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yoshida, Kiyoyuki, Kuwahara, Hiroichi, Iida, Kazuyuki
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): BOWSER, BARRY
• Application Number:
  US07/952,651
• Time in Patent Office: 1,478 Days
• Field of Search: 371/22.3, 371/22.6, 324/158 R, 324/756-762
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's

Abstract

A semiconductor circuit element device with an arrangement for testing the device including a plurality of first logic circuits provided in correspondence with internal line groups which are formed by grouping the internal lines into a plurality of groups, a plurality of internal lines belonging to a group in question constituting the input lines of the plurality of first logic circuits, for outputting an active output signal when all of the inputs represent active signals and outputting an inactive output signal when at least one of the inputs represents an inactive signal; and a second logic circuit constituted by one or more stages of circuit structures, for receiving the outputs of the first logic circuits and sending out an output signal such that the output signal in the case where all of the inputs are inactive output signals is different from the output signal in the case where at least one of the inputs is an active output signal.

Claims

1. A semiconductor circuit device having an arrangement for testing said semiconductor circuit device when mounted on a printed circuit board, said semiconductor circuit device comprising:

a plurality of connection pins, each of said connection pins to be connected to conductor connection portions of a printed circuit board,

a system circuit,

internal lines to be connected to said system circuit and to said connection pins,

a plurality of first logic circuits provided in correspondence with internal line groups which are formed by grouping said internal lines into a plurality of groups, a plurality of internal lines belonging to a group in question constituting the input lines of said plurality of first logic circuits, for outputting an active output signal when all of the inputs represent active signals and outputting an inactive output signal when at least one of the inputs represents an inactive signal;

a second logic circuit constituted by one or more stages of circuit structures, for receiving the outputs of said first logic circuits and sending out an output signal so that the output signal when all of said inputs are inactive output signals is different from the output signal when at least one of said inputs is an active output signal;

wherein said arrangement for testing said semiconductor circuit device performs a group selection process for selecting one group as the group to be tested from the groups of internal lines;

inactive signal supply means for supplying an inactive signal through said conductor connecting portions of a printed circuit board to at least one internal line in the lines of the groups which are not selected in said group selection process;

active signal supply responsive output signal checking means for supplying active signals through said conductor connecting portions of a printed circuit board to the internal lines of the group selected in said group selection process and checking the signal output from the semiconductor circuit element in response to the supply of the active signals, and

inactive signal supply responsive output signal checking means for selecting internal lines successively from the internal lines of the group selected in said group selection process, supplying inactive signals through said conductor connection portions of a printed circuit board to the selected internal lines, supplying active signals through said conductor connecting portions of a printed circuit board to the remaining internal lines, and checking the signal output from the semiconductor circuit element in response to the supply of the inactive and active signals.

2. A semiconductor circuit device having an arrangement for testing said semiconductor circuit device when mounted on a printed circuit board, said semiconductor circuit element comprising:

a plurality of connection pins, each of said connection pins to be connected to conductor connecting portions of a printed circuit board,

a system circuit,

internal lines to be connected to said system circuit and to said connection pins,

a plurality of first logic circuits provided in correspondence with internal line groups which are formed by grouping said internal lines into a plurality of groups;

a plurality of internal lines belonging to a group in question constituting the input lines of said plurality of first logic circuits, for outputting an active output signal when all of the inputs represent active signals and outputting an inactive output signal when at least one of the inputs represents an inactive signal;

a second logic circuit constituted by one or more stages of circuit structures, for receiving the outputs of said first logic circuits and sending out an output signal so that the output signal when all of said inputs are inactive output signals is different from the output signal when at least one of said inputs is an active output signal;

a plurality of switch circuits arranged on the internal lines for operating to interrupt the connection between the system circuit and the first logic circuit in accordance with a control signal supplied through a control pin connected to the wiring connecting portion on the printed circuit board;

wherein said arrangement for testing said semiconductor circuit device performs a control signal supply process for supplying a control signal for interrupting the switch circuit to the conductor connecting portions connected with the control pin;

group selection means for selecting one group as the group to be tested from the groups of internal lines;

inactive signal supply means for supplying an inactive signal through said conductor connecting portions of a printed circuit board to at least one internal line in the lines of the groups which are not selected in said group selection process;

active signal supply responsive output signal checking means for supplying active signals through said conductor connecting portions of a printed circuit board to the internal lines in the groups selected in the group selection process and checking the output of the semiconductor circuit element which is sent out from the semiconductor circuit element in response to the supply of the active signals; and

inactive signal supply responsive output signal checking means for selecting internal lines successively as internal lines to be tested from the internal lines of the group which is selected in the group selection process, supplying inactive signals through said conductor connection portions of a printed circuit board to the selected internal lines, supplying active signals through said conductor connecting portions of a printed circuit board to the remaining internal lines, and checking the signal output from the semiconductor circuit element in response to the supply of the inactive and active signals.

3. A semiconductor circuit element device with an arrangement for testing the device according to claim 2, wherein said second logic circuit receives a control signal supplied through a control pin and sends out an output signal so that the output signal in the case where all of the inputs are inactive output signals is different from the output signal in the case where at least one of the inputs is an active output signal.

4. A method of a test of a semiconductor circuit element device for testing the state of connection between external pins of a semiconductor circuit element and conductor connecting portions on a printed circuit board, by using a plurality of first logic circuits provided in correspondence with internal line groups which are formed by grouping said internal lines into a plurality of groups, a plurality of internal lines belonging to a group in question constituting the input lines of said plurality of first logic circuits, for outputting an active output signal when all of the inputs represent an active signals and outputting an inactive output signal when at least one of the inputs represents an inactive signal;

and a second logic circuit constituted by one or more stages of circuit structures, for receiving the outputs of said first logic circuits and sending out an output signal so that the output signal in the case where all of said inputs are inactive output signals is different from the output signal in the case where at least one of said inputs is an active output signal, said method comprising;

a group selection process for selecting one group as the group to be tested from the groups of internal lines;

an inactive signal supply process for supplying an inactive signal through the conductor connecting portions to at least one internal line in the lines of the groups which are not selected in said group selection process;

an active signal supply responsive output signal checking process for supplying active signals through the conductor connecting portions to the internal lines of the group selected in said group selection process and checking the signal output from the semiconductor circuit element in response to the supply of the active signals; and

an inactive signal supply responsive output signal checking process for selecting internal lines successively from the internal lines of the group selected in said group selection process, supplying inactive signals through the conductor connecting portions to the selected internal lines, supplying active signals through the conductor connecting portions to the remaining internal lines, and checking the signal output from the semiconductor circuit element in response to the supply of the active and inactive signals.

8. A method of a test of a semiconductor circuit element device according to claim 4, wherein the connection between a semiconductor testing device for supplying an active/inactive signal to the semiconductor circuit element through the conductor connecting portion and the external pin of the semiconductor circuit element is such that one internal line in the internal lines of the groups is connected, in an independent form, to the semiconductor testing device, and the semiconductor testing device supplies an inactive signal which is requested to be supplied to the internal line in the group which is not selected as the group to be tested through the conductor connecting portion connected in an independent form.

5. A method of a test of a semiconductor circuit element device for testing the state of a connection between an external pin or control pin of a semiconductor circuit element and conductor connecting portions on a printed circuit board, by using a plurality of first logic circuits provided in correspondence with internal line groups which are formed by grouping said internal lines into a plurality of groups, a plurality of internal lines belonging to a group in question constituting the input lines of said plurality of first logic circuits, for outputting an active output signal when all of the inputs represent an active signals and outputting an inactive output signal when at least one of the inputs represents an inactive signal;

a second logic circuit constituted by one or more stages of circuit structures, for receiving the outputs of said first logic circuits and sending out an output signal so that the output signal in the case where all of said inputs are inactive output signals is different from the output signal in the case where at least one of said inputs is an active output signal; and

a plurality of switch circuits arranged on the internal lines for operating to interrupt the connection between the system circuit and the first logic circuit in accordance with a control signal supplied through a control pin connected to the wiring connecting portion on the printed circuit board, said method comprising;

a control signal supply process for supplying a control signal for interrupting the switch circuit to the conductor connecting portions connected with the control pin;

a group selection process for selecting one group as the group to be tested from the groups of internal lines;

an inactive signal supply process for supplying an inactive signal through the conductor connecting portions to at least one internal line in the internal lines of the groups which are not selected in the group selection process;

an active signal responsive output signal checking process for supplying active signals through the conductor connecting portions to the internal lines in the groups selected in the group selection process and checking the output of the semiconductor circuit element which is sent out from the semiconductor circuit element in response to the supply of the active signals; and

an inactive signal supply responsive output signal checking process for selecting internal lines successively as internal lines to be tested from the internal lines of the group which is selected in the group selection process, supplying inactive signals through the conductor connecting portions to the selected internal lines, supplying active signals through the conductor connecting portions to the remaining internal lines, and checking the signal output from the semiconductor circuit element in response to the supply of the inactive and active signals.

6. A method of a test of a semiconductor circuit element device according to claim 5, further comprising a control pin/conductor connecting portion connection state testing process for testing the connection state between a control pin and the corresponding conductor connecting portion by supplying a control signal to the conductor connecting portion connected to the control pin, supplying a detection signal for enabling the detection of the operation state of the interruption through the conductor connecting portion to the external pin connected to the switch circuit, and checking the state of the signals at the external pin corresponding to the supply of the detection signal.

7. A method of a test of a semiconductor circuit element device according to claim 5, further comprising a control pin/conductor connecting portion connection state testing process for testing the connection state between a control pin and the corresponding conductor connecting portion by supplying an inactive signal through the conductor connecting portion to at least one internal line in the internal lines belonging to the groups of the internal lines, supplying alternately a control signal for the interruption and a control signal for the non-interruption of the switch circuit to the conductor connecting portion connected to the control pin, and checking the output signal sent out from the semiconductor circuit element in response to the supply of the control signals.

9. A method of a test of a semiconductor circuit element device according to claim 5, wherein the connection between a semiconductor testing device for supplying an active/inactive signal to the semiconductor circuit element through the conductor connecting portion and the external pin of the semiconductor circuit element is such that one internal line in the internal lines of the groups is connected, in an independent form, to the semiconductor testing device, and the semiconductor testing device supplies an inactive signal which is requested to be supplied to the internal line in the group which is not selected as the group to be tested through the conductor connecting portion connected in an independent form.

10. A semiconductor integrated circuit device having an arrangement for testing the device comprising:

a plurality of connection pins, each connection pin comprising an input pin;

input pins to be connected to a plurality of end portions of conductors on a printed circuit board;

an internal circuit for receiving input signals, processing the received signals, and outputting the processed signals;

a test terminal coupled to said end portions of conductors on a printed circuit board, for providing a test signal;

connection quality determination means for determining a quality of connection between said plurality of end portions of conductors on a printed circuit board and said input pins, based on a test signal which is supplied through said test terminal and input through said end portions of conductors on a printed circuit board and said input pins;

wherein said test terminal and said connection quality determination means are coupled to said input pins.

11. A semiconductor integrated circuit device having an arrangement for testing the device comprising:

a plurality of connection pins, each connection pin comprising an output pin;

output pins to be connected to a plurality of end portions of conductors on a printed circuit board;

an internal circuit for receiving input signals, processing the received signals, and outputting the processed signals;

a test terminal coupled to said end portions of conductors on a printed circuit board, for providing a test signal;

connection quality determination means for determining a quality of connection between said plurality of end portions of conductors on a printed circuit board and said output pins, based on a test signal which is supplied through said test terminal and input through said end portions of conductors on a printed circuit board and said output pins;

wherein said test terminal and said connection quality determination means are coupled to said output pins; and

an output switch portion provided between said internal circuit and said output pins for connecting said internal circuit and said output pins in the usual operation state and for interrupting the connection between said internal circuit and said output pins in the case of receiving an instruction of a quality test.

12. A semiconductor integrated circuit device having an arrangement for testing the device comprising:

a plurality of connection pins, each connection pin comprising an input pin;

a test terminal coupled to said end portions of conductors on a printed circuit board, for providing a test signal;

input pins to be connected to a plurality of end portions of conductors on a printed circuit board;

an internal circuit for receiving input signals, processing the received signals, and outputting the processed signals; and

inter-pin switching means corresponding to said input pins for facilitating a test of the connection between said end portions of conductors and said input pins by interrupting the connections between adjacent input pins in the usual operation state, connecting the adjacent input pins in the case of receiving an instruction of a quality test, thereby detecting, at said test terminal coupled to said end portions of conductors on a printed circuit board, said test signal supplied through a test signal input terminal.

13. A semiconductor integrated circuit device having an arrangement for testing the device comprising:

output pins to be connected to a plurality of end portions of conductors on a printed circuit board;

test operation terminals coupled to said end portions of conductors on a printed circuit board for receiving test operation signals;

an internal circuit for receiving input signals, processing the received signals, and outputting the processed signals; and

connection quality determination means for testing a connection between said end portions of conductors and said output pins by selecting the connection between said internal circuit and said output pins in the usual operation state and selecting the connection between adjacent output pins in the case of receiving an instruction of a quality test, and for detecting, at said test operation terminals, said test operation signals supplied through said test operation terminals.

14. A semiconductor integrated circuit device with a system circuit and an arrangement for testing the semiconductor integrated circuit device when mounted on a printed circuit board having a plurality of conductors, said semiconductor integrated circuit device comprising:

a plurality of connection pins respectively corresponding to the plurality of conductors on the printed circuit board, each said connection pin comprising one of an input pin for receiving an input signal and an output pin for outputting a processed signal;

connection quality determination means for determining a quality of connection between said plurality of conductors and said plurality of respective and corresponding connection pins, said connection quality determination means determining the quality of connection based on a required relationship of selected said input signals and corresponding and selected processed signals as output through respective connection pins; and

internal lines, respectively corresponding to and inter-connecting the connection pins, the system circuit and the connection quality determination means, for transmitting signals therebetween.

15. A semiconductor circuit element device with an arrangement for testing the device, as recited in claim 14, further comprising:

a test terminal coupled to the conductors, for providing a test signal; and

wherein

said connection quality determination means determines the quality of connection between said plurality of conductors and said connection pins, based on the test signal supplied through the test terminal and the processed test signal.

16. A semiconductor circuit element device with an arrangement for testing the device, as recited in claim 15, wherein:

said test terminal and said connection quality determination means are coupled to the plurality of input pins of said connection pins.

17. A semiconductor integrated circuit device with an arrangement for testing the device as recited in claim 15,

wherein said connection pins are output pins connected to the plurality of conductors on the printed circuit board;

and

further comprising output switch means, provided between said internal lines and said output pins, for connecting said internal lines and said output pins in a usual operation state, and for interrupting said connection, between said internal lines and said output pins, in response to an instruction of a connection quality test.

18. A semiconductor integrated circuit device with an arrangement for testing the device as recited in claim 16, said connection quality determination means further comprising:

test operation terminals coupled to the conductors corresponding to input pins, for receiving test operation signals; and

said connection quality determination means further comprising;

inter-pin switch means, responsive to a control signal, corresponding to said input pins, for testing the connection between said plurality of conductors and said input pins by interrupting the connection between adjacent input pins when the control signal indicates a usual operation state, and connecting adjacent input pins when said control signal indicates a connection quality test state, and for detecting, at corresponding test operation terminals, said corresponding test operation signals.

19. A semiconductor integrated circuit device with an arrangement for testing the device as recited in claim 15, further comprising:

test operation terminals coupled to the conductors corresponding to output pins, for receiving test operation signals and wherein;

said output pins of said connection pins are connected to the plurality of conductors on the printed circuit board; and

said connection quality determination means, responsive to a control signal, tests the connection between said conductors and corresponding output pins by selecting said connection between said system circuit and said output pins when the control signal is indicative of the usual operation state and selecting said connection between adjacent output pins when the control signal is indicative of a connection quality test, and for detecting, at corresponding test operation terminals, said test operation signal supplied through said corresponding test operation terminals.

20. A semiconductor integrated circuit device as recited in claim 14, wherein

said internal lines are grouped into a plurality of internal line groups, each internal line group comprising a plurality of internal lines;

and

said connection quality determination means is coupled to said internal lines and said system circuit and further comprises;

a plurality of first logic circuits, each of said first logic circuits coupled to a corresponding one of the internal line groups, said internal line groups supplying first logic input signal to said plurality of first logic circuits, and said plurality of first logic circuits each outputting a first logic output signal, representative of an active signal when all of the said first logic input signals are representative of active signals and outputting a first output signal representative of an inactive signal when at least one of said first logic input signals is representative of an inactive signal,

a second logic circuit, comprised of at least one stage of circuit structures, for receiving said first logic output signals from said plurality of first logic circuits, and producing a second logic output signal representative of a first state when all of said received first logic output signals are representative of inactive signals and producing a second logic output signal representative of a second state when at least one of said received first logic output signals is representative of an active signal,

group selection means for selecting one of said internal line groups for testing,

inactive signal supply means for supplying an input signal representative of an inactive signal, through said conductors, to at least one of said internal lines of each internal line group which is not selected by said group selection means,

an active signal supply responsive output signal checking means for supplying input signals representative of active signals, through said conductors, to said internal lines of said selected internal line group and checking said second logic output signal in response to the supply of the input signals, and

inactive signal supply responsive output signal checking means for selecting internal lines successively, from said selected internal line group, supplying input signals representative of inactive signals through said conductors to said selected internal lines, supplying input signals representative of active signals through said conductors to said internal lines not selected, and checking said second logic output signal in response to the supply of input signals.

21. A semiconductor circuit element device as recited in claim 20, said connection quality determination means further comprising:

a plurality of switch circuits, responsive to a control signal supplied through a control pin connected to at least one of said conductors on the printed circuit board, each said plurality switch circuit coupled to a corresponding first logic circuits and said system circuit, and each switch circuit operating to interrupt the connection between said system circuit and the corresponding first logic circuit in response to the control signal; and

control signal supply means for supplying the control signal to each of said plurality of switch circuits.

22. A semiconductor circuit element device with an arrangement for testing the device according to claim 21, wherein said second logic circuit receives the control signal, and wherein said second logic circuit outputs said second logic output signal representative of a first state when all of the received said first logic output signals are representative of inactive signals and outputs said second logic signal representative of a second state when at least one of the received said first logic output signals is representative of an active signal.

23. A semiconductor integrated circuit device as recited in claim 20, wherein

said first logic circuits are AND gates;

and

said second logic circuit is an OR gate.

24. A method for testing a connection state between connection pins of a semiconductor circuit device and a plurality of conductors on a printed circuit board, said semiconductor circuit device having a plurality of connection pins, each one of the connection pins coupled to a corresponding conductor, a system circuit, internal lines coupled to the system circuit and the connection pins, said internal lines grouped into a plurality of internal line groups, each said internal line group comprised of a plurality of internal lines, a plurality of first logic circuits, each of said first logic circuits, coupled to a corresponding one of the internal line groups, receiving input signals from the corresponding internal line group and outputting a first logic output signal representative of an active signal when the first logic input signal, received by the corresponding circuit, are representative of active signals and outputting a first logic output signal representative of an inactive signal when at least one of the input signals, received by the corresponding first logic circuit, is representative of an inactive signal, and a second logic circuit of at least one stage of circuit structures, for receiving each of the first logic output signals from said plurality of first logic circuits and producing a second logic circuit output signal representative of a first state when all of said first logic output signals are representative of inactive signals, and is producing second logic circuit output signal representative of a second state when at least one of said first logic output signals is representative of an active output signal, said method comprising:

a group selection process for selecting one of said internal line groups to test;

an inactive signal supply process for supplying input signals representative of inactive signals through the conductors, to at least one of the internal lines in each internal line group which is not selected by said group selection process;

an active signal supply responsive output signal checking process for supplying active signals, through the conductors, to the each said internal line of said internal line group selected in said group selection process, and checking said second logic circuit output signal in response to the supply of input signals; and

an inactive signal supply responsive output signal checking process for selecting successively, one of said internal lines from said internal line group selected in said group selection process, supplying an input signal representative of an inactive signal, through a corresponding one of the conductors to the selected internal line, supplying input signals representative of active signals through the conductors corresponding to said internal lines not selected, and checking said second logic circuit output signal in response to the supply of the input signals.

25. A method of a test of a semiconductor circuit device as recited in claim 24, further comprising:

an interrupter process, responsive to a control signal, supplied through a control pin the control pin being one of said external pins connected to one of the conductors on the printed circuit board, said interrupter process for interrupting connections between said system circuit and said plurality of first logic circuits, by using a plurality of switches, controlled by the control signal, arranged on said internal lines, and

a control signal supply process for supplying said control signal to each of the plurality of switch circuits.

26. A method of a test of a semiconductor circuit element device according to claim 25, further comprising:

connection state testing process for testing a connection state between said control pin and a selected one of the conductors by supplying the control signal to the selected conductor, supplying a detection signal, representative of an operation state of the interrupter process, through the selected conductor to a corresponding connection pin connected to the corresponding switch circuit and checking the connection state represented by the detection signal.

27. A method of a test of a semiconductor circuit device according to claim 25, further comprising:

a connection state testing process for testing a connection state between said control pin and a selected one of the conductors, by supplying an input signal representative of an inactive signal, through said selected conductor to at least one of the internal lines belonging to each said internal line group, alternately supplying the control signal to cause corresponding switches to interrupt the connections and not interrupt the connections, and checking the second logic circuit output signal in response to the supply of said control signal.

28. A method of testing a semiconductor circuit device according to claim 24, wherein a connection between a semiconductor testing device for supplying test signals representative of active and inactive signals to each of said internal lines, through said semiconductor circuit element, said conductors and said connection pins, is such that one of said internal lines in each corresponding internal line group is connected, in an independent form, to said semiconductor testing device, and said semiconductor testing device supplies inactive test signals when said corresponding internal line group is not selected as the internal line group to be tested through corresponding conductors connected in an independent form.

29. A method of testing a semiconductor circuit device according to claim 25, wherein a connection between a semiconductor testing device for supplying test signals representative of active and inactive signals to each of said internal lines, through, said semiconductor circuit element said conductors and said connection pins, is such that one of said internal lines in each corresponding internal line group is connected, in an independent form, to said semiconductor testing device, and said semiconductor testing device supplies inactive test signals to one of internal lines in said internal line group which is not selected as said internal line group to be tested, through said conductors connected in an independent form.

30. A semiconductor integrated circuit device having a system circuit, a plurality of connection pins, internal lines respectively corresponding to and connecting the connection pins and the system circuit for transmitting signals therebetween, said semiconductor integrated circuit device being mounted on a printed circuit board having a plurality of conductors and said plurality of conductors respectively corresponding to the plurality of connection pins, said semiconductor integrated circuit device comprising:

connection quality determination means for determining a quality of connection between said plurality of conductors and said plurality of said respective and corresponding connection pins, comprising one of;

a test terminal, coupled to the plurality of conductors, for providing a test signal to the plurality of connection pins which are coupled to internal circuitry for receiving said test signal, processing said received test signal and outputting said processed test signal, and output determination means for determining, based on the output processed signal, the quality of connection;

a test terminal, coupled to the plurality of conductors, for providing a test signal to the plurality of connection pins which are coupled to internal circuitry for receiving said test signal, processing said received test signal and outputting said processed test signal, switch means, coupled to selected ones of said connection pins and said internal circuitry, responsive to a control signal, said switch means connecting said system circuit and said selected connection pins when the control signal is indicative of a usual operation state, and interrupting the connection between said system circuit and said selected connection pins when the control signal is indicative of a connection quality test state and output determination means for determining, based on the output processed signal, the quality of connection;

test operation terminals, coupled to the plurality of conductors, for providing test operation signals to the plurality of connection pins which are coupled to internal circuitry for receiving said test operation signals, processing said received test operation signals, and outputting said processed test operation signals, inter-pin switch means, coupled to selected ones of said connection pins and said internal circuitry, responsive to a control signal, said inter-pin switch means interrupting the connection between adjacent selected connection pins when the control signal indicates a usual operation state, and connecting adjacent selected connection pins when said control signal indicates a connection quality test state, and for detecting at corresponding test operation terminals, said corresponding test operation signals and output determination means for determining, based on the output processed signal, the quality of connection;

test operation terminals, coupled to the plurality of conductors, for providing test operation signals to the plurality of connection pins which are coupled to internal circuitry for receiving said test operation signals, processing said received test operation signals, and outputting said processed test operation signals, said internal circuitry selecting the connection between adjacent connection pins when the control signal indicates a usual operation state and selecting the connection between adjacent connection pins when said control signal indicates a connection quality test state and for detecting, at corresponding test operation terminals, said corresponding test operation signals, and output determination means for determining, based on the output processed signal, the quality of connection;

a plurality of first logic circuits, each of said first logic circuits coupled to a corresponding one of internal line groups, said internal line groups comprising a plurality of internal lines grouped into a plurality of internal line groups, said internal line group supplying first logic input signal to said plurality of first logic circuits, and said plurality of first logic circuits each outputting a first logic output signal, representative of an active signal when all of the said first logic input signals are representative of active signals and outputting a first output signal representative of an inactive signal when at least one of said first logic input signals is representative of an inactive signal, a second logic circuit, comprised of at least one stage of circuit structures, for receiving said first logic output signals from said plurality of first logic circuits, and producing a second logic output signal representative of a first state when all of said received first logic output signals are representative of inactive signals and producing a second logic output signal representative of a second state when at least one of said received first logic output signals is representative of an active signal, group selection means for selecting one of said internal line groups for testing, inactive signal supply means for supplying an input signal representative of an inactive signal, through said conductors, to at least one of said internal lines of each internal line group which is not selected by said group selection means, an active signal supply responsive output signal checking means for supplying input signals representative of active signals, through said conductors, to said internal lines of said selected internal line group and checking said second logic output signal in response to the supply of the input signals, and inactive signal supply responsive output signal checking means for selecting internal lines successively, from said selected internal line group, supplying input signals representative of inactive signals through said conductors to said selected internal lines, supplying input signals representative of active signals through said conductors to said internal lines not selected and checking said second logic output signal in response to the supply of input signals;

a plurality of first logic circuits, each of said first logic circuits coupled to a corresponding one of internal line groups, said internal line groups comprising a plurality of internal lines grouped into a plurality of internal line groups, said internal line group supplying first logic input signal to said plurality of first logic circuits, and said plurality of first logic circuits each outputting a first logic output signal, representative of an active signal when all of the said first logic input signals are representative of active signals and outputting a first output signal representative of an inactive signal when at least one of said first logic input signals is representative of an inactive signal, a second logic circuit, comprised of at least one stage of circuit structures, for receiving said first logic output signals from said plurality of first logic circuits, and producing a second logic output signal representative of a first state when all of said received first logic output signals are representative of inactive signals and producing a second logic output signal representative of a second state when at least one of said received first logic output signals is representative of an active signal, group selection means for selecting one of said internal line groups for testing, inactive signal supply means for supplying an input signal representative of an inactive signal, through said conductors, to at least one of said internal lines of each internal line group which is not selected by said group selection means, an active signal supply responsive output signal checking means for supplying input signals representative of active signals, through said conductors, to said internal lines of said selected internal line group and checking said second logic output signal in response to the supply of the input signals, inactive signal supply responsive output signal checking means for selecting internal lines successively, from said selected internal line group, supplying input signals representative of inactive signals through said conductors to said selected internal lines, supplying input signals representative of active signals through said conductors to said internal lines not selected, and checking said second logic output signal in response to the supply of input signals, and a plurality of switch circuits, responsive to a control signal supplied through a control pin connected to at least one of said conductors on the printed circuit board, each said plurality switch circuit coupled to a corresponding first logic circuits and said system circuit, and each switch circuit operating to interrupt the connection between said system circuit and the corresponding first logic circuit in response to the control signal; and

control signal supply means for supplying the control signal to each of said plurality of switch circuits; and

a plurality of first logic circuits, each of said first logic circuits coupled to a corresponding one of internal line groups, said internal line groups comprising a plurality of internal lines grouped into a plurality of internal line groups, said internal line group supplying first logic input signal to said plurality of first logic circuits, and said plurality of first logic circuits each outputting a first logic output signal, representative of an active signal when all of the said first logic input signals are representative of active signals and outputting a first output signal representative of an inactive signal when at least one of said first logic input signals is representative of an inactive signal, a second logic circuit, comprised of at least one stage of circuit structures, for receiving said first logic output signals from said plurality of first logic circuits, and producing a second logic output signal representative of a first state when all of said received first logic output signals are representative of inactive signals and producing a second logic output signal representative of a second state when at least one of said received first logic output signals is representative of an active signal, group selection means for selecting one of said internal line groups for testing, inactive signal supply means for supplying an input signal representative of an inactive signal, through said conductors, to at least one of said internal lines of each internal line group which is not selected by said group selection means, an active signal supply responsive output signal checking means for supplying input signals representative of active signals, through said conductors, to said internal lines of said selected internal line group and checking said second logic output signal in response to the supply of the input signals, inactive signal supply responsive output signal checking means for selecting internal lines successively, from said selected internal line group, supplying input signals representative of inactive signals through said conductors to said selected internal lines, supplying input signals representative of active signals through said conductors to said internal lines not selected, and checking said second logic output signal in response to the supply of input signals, and a plurality of switch circuits, responsive to a control signal supplied through a control pin connected to at least one of said conductors on the printed circuit board, each said plurality switch circuit coupled to a corresponding first logic circuits and said system circuit, and each switch circuit operating to interrupt the connection between said system circuit and the corresponding first logic circuit in response to the control signal; and

control signal supply means for supplying the control signal to each of said plurality of switch circuits; and

wherein said second logic circuit receives the control signal, and wherein said second logic circuit outputs said second logic output signal representative of a first state when all of the received said first logic output signals are representative of inactive signals and outputs said second logic signal representative of a second state when at least one of the received said first logic output signals is representative of an active signal.

31. A semiconductor integrated circuit device having a system circuit, a plurality of connection pins, internal lines respectively corresponding to and connecting the connection pins and the system circuit for transmitting signals therebetween, said semiconductor integrated circuit device being mounted on a printed circuit board having a plurality of conductors and said plurality of conductors respectively corresponding to the plurality of connection pins, said semiconductor integrated circuit device comprising:

connection quality determination means for determining in a sequence of tests, in any order, a quality of connection between said plurality of conductors and said plurality of said respective and corresponding connection pins, said connection quality determination means further comprising;

in a first test, a test terminal, coupled to the plurality of conductors, for providing a test signal, internal circuitry for receiving said test signal, processing said received test signal and outputting said processed test signal, and output determination means for determining, based on the output processed signal, the quality of connection;

in a second test, a test terminal, coupled to the plurality of conductors, for providing a test signal, internal circuitry for receiving said test signal, processing said received test signal and outputting said processed test signal, switch means, coupled to selected ones of said connection pins and said internal circuitry, responsive to a control signal, said switch means connecting said system circuit and said selected connection pins when the control signal is indicative of a usual operation state, and interrupting the connection between said system circuit and said selected connection pins when the control signal is indicative of a connection quality test state and output determination means for determining, based on the output processed signal, the quality of connection;

in a third test, test operation terminals, coupled to the plurality of conductors, for providing test operation signals, internal circuitry for receiving said test operation signals, processing said received test operation signals, and outputting said processed test operation signals, inter-pin switch means, coupled to selected ones of said connection pins and said internal circuitry, responsive to a control signal, said inter-pin switch means interrupting the connection between adjacent selected connection pins when the control signal indicates a usual operation state, and connecting adjacent selected connection pins when said control signal indicates a connection quality test state, and for detecting at corresponding test operation terminals, said corresponding test operation signals and output determination means for determining, based on the output processed signal, the quality of connection;

in a fourth test, test operation terminals, coupled to the plurality of conductors, for providing test operation signals, internal circuitry for receiving said test operation signals, processing said received test operation signals, and outputting said processed test operation signals, said internal circuitry selecting the connection between adjacent connection pins when the control signal indicates a usual operation state and selecting the connection between adjacent connection pins when said control signal indicates a connection quality test state and for detecting, at corresponding test operation terminals, said corresponding test operation signals, and output determination means for determining, based on the output processed signal, the quality of connection;

in a fifth test, a plurality of first logic circuits, each of said first logic circuits coupled to a corresponding one of internal line groups, said internal line groups comprising a plurality of internal lines grouped into a plurality of internal line groups, said internal line group supplying first logic input signal to said plurality of first logic circuits, and said plurality of first logic circuits each outputting a first logic output signal, representative of an active signal when all of the said first logic input signals are representative of active signals and outputting a first output signal representative of an inactive signal when at least one of said first logic input signals is representative of an inactive signal, a second logic circuit, comprised of at least one stage of circuit structures, for receiving said first logic output signals from said plurality of first logic circuits, and producing a second logic output signal representative of a first state when all of said received first logic output signals are representative of inactive signals and producing a second logic output signal representative of a second state when at least one of said received first logic output signals is representative of an active signal, group selection means for selecting one of said internal line groups for testing, inactive signal supply means for supplying an input signal representative of an inactive signal, through said conductors, to at least one of said internal lines of each internal line group which is not selected by said group selection means, an active signal supply responsive output signal checking means for supplying input signals representative of active signals, through said conductors, to said internal lines of said selected internal line group and checking said second logic output signal in response to the supply of the input signals, and inactive signal supply responsive output signal checking means for selecting internal lines successively, from said selected internal line group, supplying input signals representative of inactive signals through said conductors to said selected internal lines, supplying input signals representative of active signals through said conductors to said internal lines not selected and checking said second logic output signal in response to the supply of input signals;

in a sixth test, a plurality of first logic circuits, each of said first logic circuits coupled to a corresponding one of internal line groups, said internal line groups comprising a plurality of internal lines grouped into a plurality of internal line groups, said internal line group supplying first logic input signal to said plurality of first logic circuits, and said plurality of first logic circuits each outputting a first logic output signal, representative of an active signal when all of the said first logic input signals are representative of active signals and outputting a first output signal representative of an inactive signal when at least one of said first logic input signals is representative of an inactive signal, a second logic circuit, comprised of at least one stage of circuit structures, for receiving said first logic output signals from said plurality of first logic circuits, and producing a second logic output signal representative of a first state when all of said received first logic output signals are representative of inactive signals and producing a second logic output signal representative of a second state when at least one of said received first logic output signals is representative of an active signal, group selection means for selecting one of said internal line groups for testing, inactive signal supply means for supplying an input signal representative of an inactive signal, through said conductors, to at least one of said internal lines of each internal line group which is not selected by said group selection means, an active signal supply responsive output signal checking means for supplying input signals representative of active signals, through said conductors, to said internal lines of said selected internal line group and checking said second logic output signal in response to the supply of the input signals, inactive signal supply responsive output signal checking means for selecting internal lines successively, from said selected internal line group, supplying input signals representative of inactive signals through said conductors to said selected internal lines, supplying input signals representative of active signals through said conductors to said internal lines not selected, and checking said second logic output signal in response to the supply of input signals, and a plurality of switch circuits, responsive to a control signal supplied through a control pin connected to at least one of said conductors on the printed circuit board, each said plurality switch circuit coupled to a corresponding first logic circuits and said system circuit, and each switch circuit operating to interrupt the connection between said system circuit and the corresponding first logic circuit in response to the control signal; and

control signal supply means for supplying the control signal to each of said plurality of switch circuits; and

in a seventh test, a plurality of first logic circuits, each of said first logic circuits coupled to a corresponding one of internal line groups, said internal line groups comprising a plurality of internal lines grouped into a plurality of internal line groups, said internal line group supplying first logic input signal to said plurality of first logic circuits, and said plurality of first logic circuits each outputting a first logic output signal, representative of an active signal when all of the said first logic input signals are representative of active signals and outputting a first output signal representative of an inactive signal when at least one of said first logic input signals is representative of an inactive signal, a second logic circuit, comprised of at least one stage of circuit structures, for receiving said first logic output signals from said plurality of first logic circuits, and producing a second logic output signal representative of a first state when all of said received first logic output signals are representative of inactive signals and producing a second logic output signal representative of a second state when at least one of said received first logic output signals is representative of an active signal, group selection means for selecting one of said internal line groups for testing, inactive signal supply means for supplying an input signal representative of an inactive signal, through said conductors, to at least one of said internal lines of each internal line group which is not selected by said group selection means, an active signal supply responsive output signal checking means for supplying input signals representative of active signals, through said conductors, to said internal lines of said selected internal line group and checking said second logic output signal in response to the supply of the input signals, inactive signal supply responsive output signal checking means for selecting internal lines successively, from said selected internal line group, supplying input signals representative of inactive signals through said conductors to said selected internal lines, supplying input signals representative of active signals through said conductors to said internal lines not selected, and checking said second logic output signal in response to the supply of input signals, and a plurality of switch circuits, responsive to a control signal supplied through a control pin connected to at least one of said conductors on the printed circuit board, each said plurality switch circuit coupled to a corresponding first logic circuits and said system circuit, and each switch circuit operating to interrupt the connection between said system circuit and the corresponding first logic circuit in response to the control signal; and

control signal supply means for supplying the control signal to each of said plurality of switch circuits; and

wherein said second logic circuit receives the control signal, and wherein said second logic circuit outputs said second logic output signal representative of a first state when all of the received said first logic output signals are representative of inactive signals and outputs said second logic signal representative of a second state when at least one of the received said first logic output signals is representative of an active signal.