Voltage range tolerant CMOS output buffer with reduced input capacitance

• US 5,565,794 A
• Filed: 06/23/1995
• Issued: 10/15/1996
• Est. Priority Date: 06/23/1995
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Porter, John D.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/494,271
• Time in Patent Office: 480 Days
• Field of Search: 326/57-58, 326/80-81, 326/83, 326/86-87, 326/17, 326/30, 326/112, 326/117, 326/119, 326/120, 326/121
• US Class Current: 326/81
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 19/09429 one of the states being the high impedance or floating state

Abstract

A tri-state CMOS output buffer is provided which exhibits a relatively low input capacitance and tolerance to a range of operating voltages. The output buffer includes a PUP input, a PD input and an output. The output buffer includes a source follower circuit coupled to the PUP input such that the output of the source follower generally follows transitions in the PUP input signal. The source follower output is the buffer output. A pull-down transistor is coupled between the buffer output and ground to pull-down the output voltage when the PD signal goes high. A pull-up transistor and an isolation transistor are coupled in series to form a series coupled circuit. This series-coupled circuit is coupled in parallel with the source follower. The pull-up transistor pulls up the voltage on the buffer output when the PUP input signal goes high. The isolation transistor is switchable to an off state to isolate a parasitic diode associated with the pull-up transistor. A control circuit is coupled to the buffer output and the PUP input to monitor the buffer output and the PUP input to turn off the isolation transistor when the buffer output is in a tri-state condition and the buffer output is driven high by an external device. Otherwise, the control circuit causes the isolation transistor to remain on. In this manner, isolation transistor switching is significantly reduced and the capacitive load presented to the PUP input signal is substantially lowered.

Claims

1. A tri-state output buffer comprising:

a PUP input, a PD input and an output, the PUP input receiving a PUP input signal, the PD input receiving a PD input signal;

a source follower circuit coupled to the PUP input and the output such that the output exhibits an output voltage which generally follows the PUP input signal;

a pull-down transistor coupled to the PD input and the output to pull-down the output voltage when the PD input signal goes high and the PUP signal goes low;

a series-coupled circuit including a pull-up transistor coupled in series with an isolation transistor, the series-coupled circuit being coupled in parallel with the source follower circuit, the pull-up transistor being coupled to the PUP input to pull up the output voltage when the PUP input signal goes high, the pull-up transistor including a parasitic diode, the isolation transistor being a depletion mode NMOS transistor which is switchable to an off state to provide isolation of the parasitic diode from the output; and

a control circuit, coupled to the output and the PUP input and to the isolation transistor, for monitoring the output voltage and the PUP input voltage and for controlling the isolation transistor to turn off the isolation transistor when the output is in a tri-state condition and the output is driven high, the control circuit otherwise permitting the isolation transistor to remain on, whereby input capacitance at the PUP input is effectively reduced.

2. The tri-state output buffer of claim 1 wherein the control circuit is a NAND gate having a first input terminal coupled to the PUP input, a second input terminal coupled to the output and an output terminal coupled to a control terminal of the isolation transistor.

3. The tri-state output buffer of claim 1 further comprising an inverter coupled between the PUP input and the control circuit.

4. The tri-state output buffer of claim 1 wherein the pull-up transistor comprises an enhancement mode PMOS transistor.

5. The tri-state output buffer of claim 1 wherein the source follower circuit comprises an enhancement mode NMOS transistor.

6. The tri-state output buffer of claim 1 wherein the pull-down transistor comprises an enhancement mode NMOS transistor.

7. A tri-state output buffer comprising:

a PUP input, a PD input and a buffer output, the PUP input receiving a PUP input signal, the PD input receiving a PD input signal;

an inverter coupled to the PUP input to provide a /PUP signal;

a source follower circuit coupled to the PUP input and the buffer output such that the buffer output exhibits a buffer output voltage which generally follows the PUP input signal;

a pull-down transistor coupled to the PD input and the buffer output to pull-down the buffer output voltage when the PD input signal goes high and the PUP signal goes low;

a series-coupled circuit including a pull-up transistor coupled in series with an isolation transistor, the isolation transistor including a gate, the series-coupled circuit being coupled in parallel with the source follower circuit,

the pull-up transistor being coupled to the inverter to receive the /PUP signal and to pull up the buffer output voltage when the PUP input signal goes high, the pull-up transistor including a parasitic diode, the isolation transistor being a depletion mode NMOS transistor which is switchable to an off state to provide isolation of the parasitic diode from the buffer output; and

a NAND gate including a first NAND input, a second NAND input and a NAND output, the first NAND input being coupled to the inverter to receive the PUP signal, the second NAND input being coupled to the buffer output, the NAND output being coupled to the gate of the isolation transistor, the NAND gate monitoring the buffer output voltage and the /PUP signal and for controlling the isolation transistor to turn off the isolation transistor when the buffer output is in a tri-state condition and the buffer output is driven high, the NAND gate otherwise permitting the isolation transistor to remain on, whereby input capacitance at the PUP input is effectively reduced.

8. The tri-state output buffer of claim 7 wherein the pull-up transistor comprises an enhancement mode PMOS transistor.

9. The tri-state output buffer of claim 7 wherein the source follower circuit comprises an enhancement mode NMOS transistor.

10. The tri-state output buffer of claim 7 wherein the pull-down transistor comprises an enhancement mode NMOS transistor.

11. A tristate output buffer comprising:

a pullup PMOS transistor having a source terminal coupled to a power supply line, a drain terminal and a gate terminal coupled to a pullup input signal line;

an isolation NMOS depletion mode transistor having a source terminal coupled to an output pad, a drain terminal coupled to the drain terminal of the pullup PMOS transistor and a gate terminal;

a pulldown NMOS transistor having a source terminal coupled to a reference line, a drain terminal coupled to the source terminal of the isolation NMOS transistor and the output pad, and a gate terminal coupled to a pulldown input signal line;

a source follower NMOS transistor having a source terminal coupled to the output pad, a drain terminal coupled to the power supply line and a gate terminal coupled to the pullup input signal line;

a parasitic diode inherently formed in the tristate output buffer; and

a control circuit having a first input terminal coupled to the pullup input signal line, a second input terminal coupled to the output pad and an output terminal coupled to the gate terminal of the isolation NMOS depletion mode transistor, the control circuit for switching the isolation NMOS depletion mode transistor so that the output terminal is isolated from the parasitic diode.

12. The tristate output buffer according to claim 11 wherein the control circuit is a NAND gate.

13. The tristate output buffer according to claim 11 further comprising an inverter coupled between the pullup input signal line and the control circuit.

14. The tristate output buffer according to claim 11 wherein the pullup PMOS transistor is an enhancement mode PMOS transistor.

15. The tristate output buffer according to claim 11 wherein the source follower NMOS transistor is an enhancement mode NMOS transistor.

16. The tristate output buffer according to claim 11 wherein the pulldown NMOS transistor is an enhancement mode NMOS transistor.