Computational circuit

• US 5,565,809 A
• Filed: 06/06/1995
• Issued: 10/15/1996
• Est. Priority Date: 09/20/1993
• Status: Expired due to Fees

• Current Assignee: YOZAN, Inc.
• Original Assignee: Sharp Corporation (Hon Hai Precision Industry Co., Ltd.), YOZAN, Inc.
• Inventors: Yamamoto, Makoto, Takatori, Sunao, Shou, Guoliang
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Lam, T.
• Application Number:
  US08/468,421
• Time in Patent Office: 497 Days
• Field of Search: 327/355-359, 327/361, 327/363, 327/331, 327/332, 364/606, 364/754
• US Class Current: 327/356
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: G06G 7/14 for addition or subtraction of vector quantities G06G7/22 ; computing the average by addition; differential amplifiers H03F3/45
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence

Abstract

A computational circuit that includes a pair of operational amplifiers, wherein one of the amplifiers receives an analog input voltage. Switching circuits are provided to selectively connect the outputs of the operational amplifiers to a common node and to respective inputs thereof via feedback lines. Capacitors are provided at the common node. A digital signal actuates the switching circuits so that one switching circuit is opened when the other is closed.

Claims

1. A computational circuit comprising:

a first operational amplifier having a first inverting input, a first non-inverting input and a first output, said first operational amplifier receiving an analog input voltage at said first non-inverting input;

second operational amplifier having a second inverting input, a second non-inverting input and a second output, said second non-inverting input being connected to ground;

a first switching circuit connected to said first output of said first operational amplifier;

a second switching circuit connected to said second output of said second operational amplifier;

a first capacitance connected through said first switching circuit to said first output of said first operational amplifier;

a second capacitance connecting said first capacitance to said ground;

a first feed back line connecting a juncture of said first capacitance and said second capacitance to said first inverted input of said first operational amplifier;

a second feed back line connecting said second output of said second operational amplifier to said second inverted input of said second operational amplifier;

a third capacitance connected to said first output of said first operational amplifier though said first switching circuit and connected to said output of said second operational amplifier through said second switching circuit; and

a digital signal actuating said first switching circuit and said second switching circuit so that one of said first switching circuit and said second switching circuit is opened when a remaining other of said first switching circuit and said second switching circuit is closed.