Phase ambiguity removing device

• US 5,566,184 A
• Filed: 03/21/1994
• Issued: 10/15/1996
• Est. Priority Date: 03/19/1993
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Ooi, Tomoyuki
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): CHUNG, PHUNG M
• Application Number:
  US08/215,480
• Time in Patent Office: 939 Days
• Field of Search: 371/5.1, 371/25.1, 371/47.1, 371/5.4, 371/42, 371/57.1, 371/57.2, 375/108, 375/10, 370/13, 370/14, 370/15, 370/16, 370/17
• US Class Current: 714/704
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

A phase ambiguity removing device for determining the proper phase of the Pch, Qch data demodulated by a receive side demodulator of a Quadrature Phase Shift Keying (QPSK) system includes a second phase information controller for determining the most probable phase of the received signals when detection of synchronizing words fail in the Pch and Qch signals.

Claims

1. A phase ambiguity removing device comprising:

counting means for counting a number of error bits of received synchronizing words of two predetermined phases among four phases due to phase slip of a received QPSK signal;

first phase information controlling means for generating a first phase information indicative of the phases for which the received synchronizing words are detected on the basis of said number of error bits detected by said counting means;

second phase information controlling means for generating a second phase information indicative of the phases for which a probability of existence of said synchronizing word is high when the received synchronizing words cannot be detected on the basis of said number of error bits detected by said counting means;

selecting means for selecting a phase information from said first phase information controller when the received synchronizing words are detected or from said second phase information controller when the received synchronizing words cannot be detected; and

removing means for removing phase ambiguity from received signals on the basis of an output of said selecting means.

2. The removing device as claimed in claim 1, wherein said second phase information controlling means further comprises:

means for determining the phase whose error number is minimum as the most probable phase on the basis of comparing said synchronizing word errors in said respective phases.

3. The removing device as claimed in claim 2, said removing device further comprising:

controlling means for controlling said selecting means so that said selecting means outputs said first phase information when said synchronizing word is detected and outputs said second phase information when said synchronizing word or said most probable phase is not detected.

4. The removing device as claimed as claim 1, wherein said counting means comprises:

first calculating means for calculating a first error number in a first phase representing a comparison of a first reference synchronizing word in said first phase with said received synchronizing word; and

second calculating means for calculating a second error number in a second phase representing a comparison of a second reference synchronizing word in said second phase with said received synchronizing word.

5. The removing device as claimed as claim 4, wherein said second phase information controlling means comprises:

first comparing means for comparing said first error number with said second error number;

second comparing means for comparing said first error number with an error number corresponding to an inversion of said second phase; and

logic means for determining which phase of four phases is the most probable, from results of the two comparisons in said first and second comparing means.

6. A method for controlling a phase ambiguity, the method comprising the steps of:

(a) counting a number of error bits of synchronizing words of two predetermined phases among four phases due to a received QPSK signal;

(b) generating a first phase information indicative of phases for which the received synchronizing word is detected on the basis of said number of error bits detected by said counting means;

(c) generating a second phase information indicative of phases in which a probability of existence of said synchronizing word is high when the received synchronizing words cannot be detected on the basis of said number of error bits detected by said counting means;

(d) selecting a phase information from said first phase information controller when the received synchronizing words are detected or from said second phase information controller when the received synchronizing words cannot be detected,.

(e) removing phase ambiguity from received signals on the basis of said first and said second phase informations.