Fast acquisition clock recovery system

• US 5,566,204 A
• Filed: 05/02/1994
• Issued: 10/15/1996
• Est. Priority Date: 05/02/1994
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor International Incorporated (ON Semiconductor Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Guedj, Jack P., Moy, Sam H., Kardontchik, Jaime E.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Le, Amanda T.
• Application Number:
  US08/236,939
• Time in Patent Office: 897 Days
• Field of Search: 375/219, 375/259, 375/294, 375/316, 375/324, 375/326, 375/327, 375/354, 375/357, 375/373, 375/374, 375/375, 375/376, 455/13.2, 455/75, 455/76, 455/84, 455/86, 455/87, 455/255-260, 455/264, 455/265, 455/315, 455/316, 331/11, 331/14, 331/17, 331/25, 327/2, 327/5, 327/39, 327/41, 327/141, 327/155-157, 327/144-148
• US Class Current: 375/219
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A transceiver integrated circuit including a transmitter section having a phase-locked loop with an oscillator to provide an output at a predetermined transmission frequency, and a receiver section having a phase-locked loop with an oscillator used to provide a recovered clock from an incoming data signal. In a second mode when no incoming data is being received, the receiver oscillator is controlled in accordance with the transmitter oscillator to operate the receiver oscillator at the expected frequency of future data. Therefore, when data is received, the receiver oscillator is at the same approximate frequency as the incoming data thereby enabling fast acquisition by merely adjusting the phase of the receiver oscillator to the incoming data. In particular, the receiver and transmitter oscillators are identical current controlled oscillators that are operated in the second mode at the same approximate frequency by feeding the receiver oscillator with a current that is substantially equal to the loop current controlling the transmitter oscillator. Further, to provide higher slaving accuracy, a frequency detector is used to compare the outputs of the receiver and transmitter oscillators in the second mode, and to control the receiver oscillator into frequency synchronism with the transmitter oscillator.

Claims

1. A communications circuit comprising:

a transmitter locked loop comprising a transmitter oscillator for providing an output at a predetermined frequency;

a receiver phase-locked loop comprising a receiver oscillator and means for controlling said receiver oscillator in response to an incoming data signal to recover the clock of said incoming data signal; and

means operable in the absence of an incoming data signal for operating said receiver oscillator at an expected frequency of a future incoming data signal to minimize the receiver oscillator frequency shift required to operate the receiver oscillator at the frequency of said future incoming data signal once received, said operating means comprising means for controlling said receiver oscillator in accordance with said transmitter oscillator.

2. The communications circuit recited in claim 1 wherein said transmitter locked loop, said receiver phase-locked loop, and said operation means are disposed on an integrated circuit.

3. The communications circuit recited in claim 1 wherein said operating means comprises a frequency detector responsive to an output of said transmitter oscillator at said predetermined frequency and an output of said receiver oscillator, said receiver oscillator being responsive to said frequency detector in the absence of an incoming data signal.

4. The communications circuit recited in claim 3 wherein said transmitter and receiver oscillators are current controlled oscillators, and said receiver oscillator is responsive to locked loop current fed back to said transmitter oscillator.

5. A communications system, comprising:

a transmitter comprising a transmitter oscillator responsive to a reference signal for providing an output at a predetermined frequency, said transmitter further comprising a locked loop comprising a frequency detector responsive to said reference signal and said output of said transmitter oscillator, said transmitter oscillator being responsive to an output of said frequency detector;

a receiver comprising a receiver oscillator;

means for controlling said receiver oscillator in accordance with said transmitter oscillator during a first mode of operation when no input data signal is being received by said receiver to cause an output of said receiver oscillator to be substantially at said predetermined frequency during said first mode of operation, said first mode controlling means comprising a second frequency detector responsive to said output of said receiver oscillator and said output of said transmitter oscillator, said receiver oscillator being responsive to an output of said second frequency detector during said first mode of operation; and

means for controlling said receiver oscillator in response to an input data signal during a second mode of operation when said input data signal is being received by said receiver to recover the clock of said input data signal.

6. The system recited in claim 5 wherein said transmitter oscillator is responsive to a total feedback current in said transmitter locked loop, and said first mode controlling means further comprises a second locked loop comprising a current adder responsive to a loop correction feedback current and a current equal to said total feedback current of said transmitter locked loop, said receiver oscillator being responsive to a sum current from said current adder.

7. The system recited in claim 5 wherein said second mode controlling means comprises a phase-locked loop comprising said receiver oscillator and a phase detector responsive to said output of said receiver oscillator and an exclusive OR of said input data signal and a delay of said input data signal, said receiver oscillator being responsive to an output of said phase detector during said second mode of operation.

8. The system recited in claim 7 wherein said receiver further comprises means for detecting input data signal transitions and means responsive to said transition detecting means for multiplexing between said output of said second frequency detector and said output of said phase detector, said receiver oscillator being responsive to an output of said multiplexing means.

9. The system recited in claim 5 wherein said receiver and transmitter oscillators are current controlled oscillators.

10. A communication system, comprising:

a transmitter comprising a locked loop comprising a frequency detector and an oscillator responsive to an output of said frequency detector wherein said frequency detector is responsive to an output from said oscillator and a reference clock to drive said output of said oscillator to a predetermined frequency; and

a receiver comprising an oscillator controlled in accordance with said transmitter oscillator during a first mode of operation when no input data signal is being received by said receiver to cause an output of said receiver oscillator to be at substantially the same frequency as said output of said transmitter oscillator during said first mode of operation, said receiver oscillator being controlled in response to an input data signal during a second mode of operation when said input data signal is being received by said receiver to generate a recovered clock for said input data signal, said receiver further comprising a first locked loop operable during said first mode of operation, said first locked loop comprising a second frequency detector, a multiplexer, and said receiver oscillator wherein said second frequency detector is responsive to said outputs of said transmitter and receiver oscillators, said multiplexer is responsive to an output of said second frequency detector, and said receiver oscillator is responsive to an output of said multiplexer.

11. The system recited in claim 10 wherein said transmitter and receiver oscillators are current controlled oscillators.

12. The system recited in claim 10 wherein said receiver comprises a second locked loop operable during said second mode of operation, said second locked loop comprising a phase detector, said multiplexer, and said receiver oscillator, said phase detector being responsive to said output of said receiver oscillator and an exclusive OR of said input data signal and a delay of said input data signal, said multiplexer being responsive to said phase detector, and said receiver oscillator being responsive to said output of said multiplexer.

13. The system recited in claim 12 further comprising an input data signal transition detector, said multiplexer being responsive to an output of said transition detector to switch from one of said modes to the other.

14. The system recited in claim 12 wherein said transmitter locked loop comprises a current adder responsive to said transmitter frequency detector and a bias current to provide a sum current to which said transmitter oscillator is responsive.

15. The system recited in claim 14 wherein said first locked loop of said receiver comprises a current adder responsive to said output of said multiplexer and a bias current equal to said sum current of said transmitter locked loop wherein said receiver oscillator is responsive to said receiver current adder.

16. The system recited in claim 15 wherein said locked loop of said transmitter further comprises a charge pump, a loop filter, and a voltage to current converter wherein said charge pump is responsive to said transmitter frequency detector, said loop filter is responsive to said charge pump, said voltage to current converter is responsive to said loop filter, and said transmitter current adder is responsive to said voltage to current converter.

17. The system recited in claim 15 wherein said first and second locked loops of said receiver further comprise a charge pump, a loop filter, and a voltage to current converter wherein said charge pump is responsive to said multiplexer, said loop filter is responsive to said charge pump, said voltage to current converter is responsive to said loop filter, and said receiver current adder is responsive to said voltage to current converter.

18. On a transmitter and receiver integrated circuit adapted for receiving and transmitting data signals, said integrated circuit comprising:

a transmitter section comprising a phase-locked loop comprising a first frequency detector, a charge pump, a loop filter, a voltage to current converter, a current adder, and a current controlled oscillator connected in a loop, said frequency detector being responsive to an output of said current controlled oscillator and a reference clock to lock said current controlled oscillator output to a predetermined frequency; and

a receiver section comprising a 90°

delay adapted to receive an incoming non-return-to-zero data signal and provide an output signal shifted in phase by 90°

;

said receiver section further comprising an exclusive OR responsive to said incoming data signal and said phase shifted signal for providing an output signal having a frequency component of an originating clock of said non-return-to-zero incoming data signal;

said receiver section further comprising a transition detector responsive to said incoming data signal for providing a control signal indicating the presence or absence of an incoming data signal;

said receiver section further comprising first and second phase-locked loops each in common comprising a multiplexer, a charge pump, a loop filter a voltage to current converter, a current adder and a current controlled oscillator connected in series, said first phase-locked loop further comprising a second frequency detector connected between said receiver current controlled oscillator and said multiplexer, said second phase-locked loop further comprising a phase detector connected between said receiver current controlled oscillator and said multiplexer;

said multiplexer being responsive to said transition detector to select said second frequency detector as its input to activate said first phase-locked loop during a first mode of operation in the absence of an incoming data signal and to select said receiver phase detector as its input to activate said second phase-locked loop during a second mode of operation in the presence of an incoming data signal;

said second frequency detector further being responsive to said transmitter current controlled oscillator to cause said receiver current controlled oscillator to have an output frequency substantially the same as said transmitter current controlled oscillator during said first mode of operation; and

said receiver phase detector further being responsive to said exclusive OR to cause said receiver current controlled oscillator to have an output frequency substantially the same as an originating clock of said incoming data signal during said second mode of operation.

19. The integrated circuit recited in claim 18 wherein said transmitter oscillator is responsive to a total current from said transmitter current adder, and said receiver section current adder is responsive to a current substantially equal to said transmitter total current to give said receiver current controlled oscillator a free-running frequency substantially the same as the frequency of said transmitter current controlled oscillator.

20. In an integrated circuit comprising a receiver section and a transmitter section each of which comprises a phase-locked loop wherein the transmitter phase-locked loop comprises a frequency detector that locks a transmitter current controlled oscillator to provide a predetermined frequency for transmitting data signal, and the receiver phase-locked loop comprises a phase detector that locks a receiver current controlled oscillator to the originating clock frequency of an incoming data signal to generate a recovered clock, a method of operating the receiver current controlled oscillator in the absence of an incoming data signal, comprising a step of:

operating the receiver current controlled oscillator at substantially the same frequency as the transmitter current controlled oscillator in the absence of an incoming data signal to operate the receiver oscillator at the expected frequency of future incoming data to reduce the receiver oscillator frequency shift required to lock to an incoming data signal once received.

21. The method recited in claim 20 wherein said transmitter oscillator is responsive to a current in said transmitter phase locked loop, and said operating step comprises a step of controlling said receiver current controlled oscillator in response to a current substantially equal to said current in said transmitter phase-locked loop.

22. The method recited in claim 20 wherein said operating step further comprises a step of frequency detecting outputs of said transmitter oscillator and receiver oscillator, and controlling said receiver oscillator in response thereto.