Memory storage access control circuit for coupled mask-programmed microcontrollers

• US 5,566,320 A
• Filed: 07/02/1993
• Issued: 10/15/1996
• Est. Priority Date: 07/04/1992
• Status: Expired due to Fees

• Current Assignee: Klockner-Moeller GmbH
• Original Assignee: Klockner-Moeller GmbH
• Inventors: Hubert, Rolf
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Ellis, Kevin L.
• Application Number:
  US08/086,925
• Time in Patent Office: 1,201 Days
• Field of Search: 395/474, 395/200.05, 395/200.16
• US Class Current: 711/147
• CPC Class Codes: G05B 19/052 Linking several PLC's
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

The invention discloses a memory access control for coupled mask-program over microcontrollers in particular in connection with applications for memory storage programmable control in the low-cost region. The coupling of the microcontroller (MC1) and of the memory access authorization to the external program memory storage and data memory storage (7) is thereby based on a hardware wiring circuit in cooperation with a handshake provided by software. Always only one microcontroller accesses the external program memory storage/data memory storage (7) while the other microcontrollers access their internal program memory storage. The memory storage access is coordinated by the microcontroller (MC1) operating as a master through its output port (Px.y). On the hardware side the memory storage access signal (PSEN) and the address access signal (ALE) are multiplexed for the access-authorized microcontroller. The coupling based on hardware uses thereby the bidirectionally operable input-output ports (P0-P3) and their alternative functions.

Claims

1. A memory storage access control circuit for coupled mask-programmed microcontrollers comprising

an external program and data memory storage;

a common data and address bus directly connected to the external program and data memory storage;

a first microcontroller having a first plurality of bidirectionally operable ports and accessing the external program and data memory storage through the common data and address bus directly connected to the first plurality of bidirectionally operable ports;

a second microcontroller having a second plurality of bidirectionally operable ports connected respectively in parallel to the first bidirectionally operable ports of the first microcontroller by way of a pin-to-pin connection and accessing the external program and memory storage through the common data and address bus, wherein the first microcontroller is operated as a master and wherein the second microcontroller is operated as a slave relative to the first microcontroller;

a communication link furnished between the first microcontroller and the second microcontroller, wherein the communication link between the first microcontroller and the second microcontroller is controlled by software and hardware;

a multiplexer furnishing logical means connected to the external program and data memory storage and to the first microcontroller and to the second microcontroller for multiplexing external memory storage release signals and for multiplexing external address release signals of the first microcontroller and of the second microcontroller by a multiplex signal, delivered by a port used as a slave select port of the first microcontroller, representing the master, and operated as an output wherein the first microcontroller, operating as the master, decides by way of its internal mask program which one of the first microcontroller and the second microcontroller should have access authorization to the external program and data memory storage, and wherein the external memory storage release signals and the external address release signals are fed as a memory storage access signal and an address access signal to the external program and data memory storage, and wherein simultaneously the multiplex signal is used to deliver the memory storage access signal to the second microcontroller, and wherein a mask program of that one of the first microcontroller and the second microcontroller, which has not received an external memory storage access authorization, operates bidirectionally operable ports of the microcontroller without the external memory storage access authorization as high resistency inputs;

a plurality of microcontrollers up to an n-th coupled microcontroller, wherein n represents the total number of microcontrollers and is larger than 2, wherein m port outputs used as slave select port outputs of the first microcontroller operating as a master are used in order to form the multiplex signal and in order to multiplex external memory storage release signals and address release signals of those microprocessors operating as slaves, and in order to feed the external memory storage release signals and the address release signals to the external program and data memory storage as memory storage access signal and as address access signal, wherein n is smaller than 2m, wherein the multiplex signal accesses the logical means, which are provided as n to 1 multiplexer, and wherein the multiplex signal simultaneously commands the selected microcontroller to access the external program and data memory storage through slave select port inputs of the selected microcontroller;

wherein the mask code of each one of the plurality of microcontrollers beginning with the second microcontroller, coupled to the master microcontroller, operates an acknowledgment port connector of each one of the plurality of microcontrollers beginning with the second microcontroller as an input with a pull-up resistor, and wherein the mask code switches the acknowledgment port connector as an output during the external memory storage access in order to deliver a message to a master of an external memory storage access;

wherein the first microcontroller representing the master receives at its acknowledgment port connector a handshaking signal from a microcontroller of the plurality of microcontrollers beginning with the second microcontroller, wherein said handshaking signal is furnished to the master for the external memory storage access, and wherein this handshaking signal confirms the memory storage access and the end of the memory storage access of the slave to the master.

2. The memory storage access control circuit according to claim 1, further comprising

terminal connector strips to be connected to memory-storage-programmable controls in the low-cost field.

3. The memory storage access control circuit according to claim 1, wherein two port outputs used as slave select port outputs of the first microcontroller operating as a master are used in order to form the multiplex signal and in order to multiplex external memory storage release signals and address release signals of those microprocessors operating as slaves, and in order to feed the external memory storage release signals and the address release signals to the external program memory storage/data memory storage as memory storage access signal and as address access signal, wherein the multiplex signal accesses the logical means, which are provided as n to 1 multiplexer, and wherein the multiplex signal simultaneously commands the selected microcontroller to access the external program memory storage/data memory storage through slave select port inputs of the selected microcontroller.

4. The memory storage access control circuit according to claim 1, wherein any microcontroller of the plurality of microcontrollers uses its ports for the external memory storage access only when it receives its external memory storage access authorization through the first microcontroller by the multiplex signal and if the memory storage release signal and the address release signal of said any microcontroller of the plurality of microcontrollers is activated.

5. The memory storage access control circuit according to claim 4, wherein each microcontroller of the plurality of microcontrollers contains a mask code, and wherein slave select ports of said each microcontroller of the plurality of microcontrollers are operated as inputs based on the respective mask code.

6. The memory storage access control circuit according to claim 1, wherein an access to the external program and data memory storage is furnished only to one of the plurality of microcontrollers while the remaining microcontrollers access their own internal memory program storage and process instructions independently from each other.

7. The memory storage access control circuit according to claim 1, wherein the first microcontroller, operating as master, contains a mask code, and wherein the first microcontroller operates a slave select port connector of the first microcontroller as an output based on the mask code of the first microcontroller.

8. The memory storage access control circuit according to claim 7, wherein the first microcontroller, operating as master, operates an acknowledgment port connector of the first microcontroller as an input based on the mask code of the first microcontroller.

9. A memory storage access control for coupled mask-programmed microcontrollers comprising

a first microcontroller (MC1) having first bidirectionally operable ports (P0 . . . P3), a first port connector (Px.y) and a first acknowledgment port connector (Pz.w) accessing directly an external program and data memory storage (7) through a common data and address bus (10);

a second microcontroller (MC2) having second bidirectionally operable ports (P0 . . . P3), a second port connector (Px.y) and a second acknowledgment port connector (Pz.w) accessing directly the external program and data memory storage through the common data and address bus wherein the first microcontroller is operated as a master and wherein the second microcontroller is operated as a slave, and wherein communication between the first microcontroller and the second microcontroller is controlled by software and hardware, wherein the first bidirectionally operable ports (P0 . . . P3), the first port connector (Px.y) and the first acknowledgment port connector (Pz.w) of the first microcontroller (MC1) and the second bidirectionally operable ports (P0 . . . P3), the second port connector (Px.y) and the second acknowledgment port connector (Pz.w) of the second microcontroller (MC2) are connected respectively in parallel by way of a pin-to-pin wiring, wherein the first microcontroller, operating as the master, decides according to an internal mask program, which one of the first microcontroller and the second microcontroller should have access authority to the external program and data memory storage (7), by multiplexing external memory storage release signals (PSEN1, PSEN2) and external address release signals (ALE1, ALE2) of the first microcontroller and of the second microcontroller by way of logical means (3,

     4) and by a multiplex signal (5), delivered by the first port connector (Px.y) of the first microcontroller and operated as an output, and wherein the external memory storage release signals (PSEN1, PSEN2) and the external address release signals (ALE1, ALE2), are fed as a memory storage access signal (PSEN) and an address access signal (ALE) to the external program and data memory storage (7), wherein simultaneously the multiplex signal (5) is used to deliver a memory storage access to the second microcontroller, and wherein the internal mask program operates bidirectionally operable ports (P0 . . . P3) of a non-authorized microcontroller as high resistency inputs;

coupled microcontrollers (MC1, MC2, MC3 . . . MCn), each having an internal memory program storage, wherein the first port connector (Px.y) and an additional port connector (Px1.y) of the first microcontroller (MC1) operating as the master are used to form the multiplex signal (5, 5a), and to order multiplexing the external memory storage release signals (PSEN1, PSEN2, PSEN3 . . . PSENn) and the address release signals (ALE1, ALE2, ALE3 . . . ALEn) of the first microcontroller and microcontrollers (MC2 . . . MCn) operating as slaves, and to order to feed the external memory storage release signals (PSEN1, PSEN2, PSEN3 . . . PSENn) and the external address release signals (ALE1, ALE2 . . . ALEn) to the external program and data memory storage (7) as the memory storage access signal (PSEN) and as the address access signal (ALE), wherein the multiplex signal (5, 5a) accesses the logical means (6, 6a), which are provided as n to 1 multiplexer, and wherein the multiplex signal (5, 5a) simultaneously is used to command one of the microcontrollers (MC1, MC2, MC3 . . . MCn) to access the external program and data memory storage wherein a command is sent through port connectors (Px.y, Px1.) of one of the microcontrollers (MC1, MC2, MC3 . . . MCn) having access authorization;

wherein mask code of each one of the microcontrollers (MC2 . . . MCn) , coupled to the master (MC1), operate acknowledgment port connector (Pz.w) of the microcontrollers (MC2 . . . MCn) as an input with a pull-up resistor, and wherein the mask code switches the acknowledgment port connector (Pz.w) as an output during the external memory storage access in order to provide a message to the first microcontroller (MC1) by requiring an external memory storage access;

wherein the master (MC1) receives at the first acknowledgment port connector (Pz.w) the message as a handshaking signal (8) from the microcontrollers (MC2 . . . MCn), furnished to the master (MC1) for the external memory storage access, wherein the handshaking signal confirms the external memory storage access and an end of the external memory storage access.

10. The memory storage access control for coupled mask-programmed microcontrollers according to claim 9, wherein one of the coupled microcontrollers (MC1 . . . MCn) uses its ports (P0-P3) for the external memory storage access only when said one of the coupled microcontrollers (MC1 . . . MCn) receives external memory storage access authorization through the first microcontroller (MC1) sent by the multiplex signal (5), furnished only for said one of the coupled microcontrollers (MC1 . . . MCn), and if the memory storage release signal (PSEN1 . . . PSENn) and the address release signal (ALE1 . . . ALEn) of said one of the coupled microcontrollers (MC1 . . . MCn) is activated.

11. The memory storage access control for coupled mask-programmed microcontrollers according to claim 9, wherein each microcontroller of the microcontrollers (MC2 . . . MCn) contains a mask code, and wherein port connectors (Px.y) of said each microcontroller of the microcontrollers (MC2 . . . MCn) are operated as inputs according to its mask code.

12. The memory storage access control for coupled mask-programmed microcontrollers according to claim 9, wherein the first microcontroller (MC1), operating as the master, contains a mask code and wherein the first microcontroller (MC1) operates the first port connector (Px.y) as an output according to the mask code of the first microcontroller.

13. The memory storage access control for coupled mask-programmed microcontrollers according to claim 12, wherein the first microcontroller (MC1), operating as the master, operates the first acknowledgment port connector (Pz.w) of the first microcontroller (MC1) as an input according to the mask code of the first microcontroller.

14. The memory storage access control for coupled mask-programmed microcontrollers according to claim 9, wherein an access to the external program and data memory storage (7) is furnished to one of the coupled microcontrollers (MC1 . . . MCn) while remaining microcontrollers of the coupled microcontrollers (MC1 . . . MCn) access their internal memory program storage based on the mask program and process instructions independently from each other.

15. A method for controlling memory storage access with microcontrollers comprising

employing an external program and data memory storage;

employing a common data and address bus connected to the external program and data memory storage;

employing a first microcontroller accessing the external program and data memory storage through the common data and address bus;

employing a second microcontroller accessing the external program and data memory storage through the common data and address bus;

operating the first microcontroller as a master;

operating the second microcontroller as a slave relative to the first microcontroller;

furnishing a communication link between the first microcontroller and the second microcontroller;

controlling the communication link between the first microcontroller and the second microcontroller by software and hardware;

furnishing a first plurality of bidirectionally operable ports at the first microcontroller;

furnishing a second plurality of bidirectionally operable ports at the second microcontroller;

connecting a plurality of independently operable port connectors to the first plurality of bidirectionally operable ports;

connecting the plurality of independently operable port connectors to the second plurality of bidirectionally operable ports, wherein the first plurality of bidirectionally operable ports, the second plurality of bidirectionally operable ports, and the plurality of independently operable port connectors for the first microcontroller and for the second microcontroller are connected respectively in parallel by way of a pin-to-pin wiring;

connecting a multiplexer furnishing logical means to the first microcontroller and to the second microcontroller;

multiplexing external memory storage release signals and multiplexing external address release signals of the first microcontroller and of the second microcontroller and based on a multiplex signal, delivered by a port used as a slave select port of the first microcontroller and operated as an output;

allowing the first microcontroller, operating as master, to decide by way of its internal mask program which one of the first microcontroller and the second microcontroller should have access authorization to the external program and data memory storage;

feeding external memory storage release signals and external address release signals as a memory storage access signal and an address access signal to the external program and data memory storage;

delivering simultaneously the memory storage access signal to the second microcontroller with the multiplex signal;

operating the bidirectionally operable ports of that one of the first microcontroller and the second microcontroller, which has not received an external memory storage access permission, as high resistency inputs according to a mask program;

employing a plurality of microcontrollers up to an n-th coupled microcontroller, wherein n is larger than 2, wherein two port outputs used as slave select port outputs of the first microcontroller operating as a master are used in order to form the multiplex signal and in order to multiplex external memory storage release signals and address release signals of those microcontrollers operating as slaves, and in order to feed the external memory storage release signals and the external address release signals to the external program and data memory storage as memory storage access signal and as address access signal, wherein the multiplex signal accesses the logical means, which are provided as n to 1 multiplexer, and wherein the multiplex signal simultaneously commands the microcontroller with the access authorization to access the external program and data memory storage through the slave select port inputs according to the mask code of the selected microcontroller;

delivering a handshaking signal from a microcontroller of the plurality of microcontrollers beginning with the second microcontroller to the first microcontroller representing the master at its acknowledgment port connector, wherein said handshaking signal is furnished to the master after receiving the external memory storage access, and wherein this handshaking signal confirms the memory storage access and the end of the memory storage access of the slave to the master.

16. The method for controlling memory storage access with microcontrollers according to claim 15, further comprising

wherein any of the microcontrollers, not authorized to the external memory storage access uses again its ports for the external memory storage access only when receives its external memory storage access authorization through the microcontroller master based on the multiplex signal, furnished only for this non-authorized microcontroller, and if the memory storage release signal and the address release signal of this non-authorized microcontroller is activated.

17. The method for controlling memory storage access with microcontrollers according to claim 15, further comprising

operating the port connector of the first microcontroller as an output based on a mask code, wherein the first microcontroller operates as a master and has the mask code incorporated.

18. The method for controlling memory storage access with microcontrollers according to claim 15,

wherein the first microcontroller operates as a master and has a mask code incorporated;

operating an acknowledgment port connector of the first microcontroller operating as the master as an input;

operating the acknowledgment port connector of the microcontrollers beginning with the second microcontroller as an input with a pull-up resistor with the mask code of each one of the plurality of microcontrollers beginning with the second microcontroller, coupled to the master microcontroller;

and wherein the mask code switches the acknowledgment port connector as an output during the external memory storage access in order to deliver a message to the master of an external memory storage access.

19. The method for controlling memory storage access with microcontrollers according to claim 15, further comprising

furnishing an access signal of the external program and data memory storage to one of the microcontrollers while remaining microcontrollers access their own internal memory program storage and process instructions independently from each other.

20. The method for controlling memory storage access with microcontrollers according to claim 15, further comprising

resetting the first microcontroller;

initializing the first plurality of bidirectionally operating ports;

accessing the external program and data memory storage;

determining a state of a first acknowledgment port of the first microcontroller and selected from a first state and a second state;

repeating the step of accessing the external program and data memory storage where a second state was determined;

accessing a first internal program and data memory storage of the first microcontroller where a first state was determined;

determining a state of a first acknowledgment port of the first microcontroller and selected from a first state and a second state;

repeating the step of accessing the first internal program and data memory storage where a first state was determined;

setting the first slave select port to a first state;

repeating the step of accessing the external program and data memory storage where a second state was determined.

21. The method for controlling memory storage access with microcontrollers according to claim 15, further comprising

resetting the second microcontroller;

initializing the second plurality of bidirectionally operating ports;

accessing a second internal program and data memory storage of the second microcontroller;

determining a state of a second slave select port of the second microcontroller and selected from a first state and a second state;

repeating the step of determining a state of the second slave select port selected from a first state and a second state where a second state was determined;

accessing the external program and data memory storage where a first state was determined;

setting a second acknowledgment port of the second microcontroller to a first state;

repeating the step of accessing the second internal program and data memory storage.