Computer apparatus including a main memory prefetch cache and method of operation thereof
First Claim
1. A computer system comprising:
- a processor;
a processor cache coupled to said processor;
a memory controller coupled to said processor;
a main memory coupled to said memory controller;
said memory controller includinga main memory prefetch cache, andcontrol means coupled to said prefetch cache for determining if a cache hit has occurred wherein a current line requested by said processor is stored in said prefetch cache, and if so, then retrieving said current line from said prefetch cache for use by said processor and overwriting said current line in said prefetch cache with a next line from said main memory, or otherwise when said prefetch cache does not contain said current line requested by said processor thus signifying a cache miss, then retrieving said current line from said main memory for use by said processor and substantially concurrently retrieving said next line from said main memory and storing said next line in said prefetch cache such that said next line is transferred to said prefetch cache prior to a request for said next line from said processor.
2 Assignments
0 Petitions
Accused Products
Abstract
A computer system is provided including a main memory prefetch cache which enhances the retrieval of instructions (code and data) stored in the main memory of a computer. The computer system includes a processor and a processor cache coupled thereto. A memory controller is coupled to the processor and includes a main memory prefetch cache. The memory controller also includes control circuitry which determines if a current line requested by the processor is stored in the prefetch cache, and if so, the memory controller retrieves the current line from the prefetch cache and provides the current line to the processor. The next line is then retrieved from the main memory and is overwritten over the current line in the prefetch cache. Otherwise, if the memory controller determines that the prefetch cache does not contain the current line requested by the processor, then the current line is retrieved from the main memory and is provided to the processor. The next line is then retrieved from the main memory and is stored in the prefetch cache at a register location which was occupied by the least recently used line in the cache. The invention includes circuitry and methodology for determining the least recently used line stored within the prefetch cache.
66 Citations
39 Claims
-
1. A computer system comprising:
-
a processor; a processor cache coupled to said processor; a memory controller coupled to said processor; a main memory coupled to said memory controller; said memory controller including a main memory prefetch cache, and control means coupled to said prefetch cache for determining if a cache hit has occurred wherein a current line requested by said processor is stored in said prefetch cache, and if so, then retrieving said current line from said prefetch cache for use by said processor and overwriting said current line in said prefetch cache with a next line from said main memory, or otherwise when said prefetch cache does not contain said current line requested by said processor thus signifying a cache miss, then retrieving said current line from said main memory for use by said processor and substantially concurrently retrieving said next line from said main memory and storing said next line in said prefetch cache such that said next line is transferred to said prefetch cache prior to a request for said next line from said processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A computer system comprising:
-
a processor; a processor cache coupled to said processor; a memory controller coupled to said processor; a main memory coupled to said memory controller; said memory controller including a main memory prefetch cache, and control means coupled to said prefetch cache for fetching from said prefetch cache a current line when requested by said processor if a cache hit occurs, and in that case substantially concurrently overwriting said current line in said prefetch cache with a next line sequentially following said current line in said main memory prior to receiving a request from said processor for said next line. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
-
21. A computer system comprising:
-
a processor; a processor cache memory which is accessible to said processor; a main memory for storing a sequence of instructions for execution by said processor; a memory controller, coupled to said processor and said main memory, for controlling access by said processor to the instructions stored in said main memory, said memory controller including a main memory prefetch cache for storing instructions prefetched from said main memory prior to a request therefor from said processor, and cache control means, coupled to said prefetch cache, for determining if a current instruction N requested by said processor is contained in said prefetch cache and, if so, retrieving said current instruction N from said prefetch cache and providing said current instruction N to said processor and retrieving a next instruction N+1 from said main memory and overwriting said current instruction N with said next instruction N+1, or otherwise when said prefetch cache does not contain a current instruction N requested by said processor, then retrieving said current instruction N from said main memory and providing said current instruction N to said processor and substantially concurrently retrieving a next instruction N+1 from said main memory and storing said next instruction N+1 in said prefetch cache memory prior to receiving a request for said next instruction from said processor. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
-
-
31. In a computer system including a processor employing a processor cache, a method of accessing a main memory comprising:
-
providing said main memory with a main memory prefetch cache including a plurality of prefetch registers for storing a plurality of lines from main memory; initiating a memory cycle to said main memory to retrieve a current line; determining if a cache hit occurs in said prefetch cache for said current line during said memory cycle; prefetching, if a cache hit occurs, said current line from said prefetch cache and then overwriting said current line in said prefetch cache with a next line from said main memory during said memory cycle; determining the least recently used line in said prefetch cache, retrieving, if a cache miss occurs, said current line from said main memory, and storing during said memory cycle, if a cache miss occurs, a next line from main memory subsequent to said current line in the particular prefetch register occupied by said least recently used line.
-
-
32. In a computer system including a processor employing a processor cache, a method of accessing a main memory comprising:
-
providing a main memory prefetch cache situated in a memory controller and coupled to said main memory; initiating a main memory cycle to retrieve a current line from said main memory; determining, by said memory controller, if said current line is stored in said prefetch cache, and if said current line is determined to be stored in said prefetch cache, then retrieving said current line from said prefetch cache and providing said current line to said processor, and retrieving a next line form said main memory and overwriting said current line in said prefetch cache with said next line during said memory cycle, and if said current line is determined not to be stored in said prefetch cache, then retrieving said current line from said main memory and providing said current line to said processor, and retrieving said next line from said main memory and storing said next line in said prefetch cache during said memory cycle. - View Dependent Claims (33, 34)
-
-
35. A method for enhancing the processing of instructions stored in a main memory of a computer system, said computer system including a processor with a processor cache memory coupled thereto, a sequence of instructions being stored in said main memory which is controlled by a memory controller, said method comprising:
-
providing said main memory with a prefetch cache memory situated in said memory controller; issuing a request, by said processor to said memory controller, for a current instruction N in said sequence of instructions stored in said main memory; determining, by said memory controller, if said current instruction N is stored in said prefetch cache memory, and if said prefetch cache memory is determined to be storing said current instruction N, then retrieving said current instruction N from said prefetch cache memory and providing said current instruction N to said processor, and, during a same memory cycle, retrieving a next instruction N+1 from said main memory and overwriting said current instruction N in said prefetch cache memory with said next instruction N+1, or if said prefetch cache memory is determined not to contain said current instruction N, then retrieving said current instruction N from said main memory and providing said current instruction N to said processor and substantially concurrently retrieving a next instruction N+1 from said main memory and storing said next instruction N+1 in said prefetch cache memory. - View Dependent Claims (36, 37)
-
-
38. A method for enhancing the processing of instructions stored in a main memory of a computer system, said computer system including a processor with a processor cache memory coupled thereto, a sequence of lines of code and data stored in said main memory which is controlled by a memory controller, said method comprising:
-
providing said main memory with a prefetch cache memory integrated within said memory controller and coupled to said main memory; issuing a request, by said processor to said memory controller, for a particular line in said sequence of lines stored in said main memory, said particular line being designated a current line; initiating a main memory cycle by said memory controller to retrieve said current line; determining, by said memory controller, if said current line is stored in said prefetch cache memory, and if said prefetch cache memory is determined to be storing said current line, then retrieving said current line from said prefetch cache memory and providing said current line to said processor and said processor cache, and modifying the main memory request begun in said initiating step to retrieve a current line+1 from said main memory and overwriting said current line in said prefetch cache memory with said current line+1 during said main memory cycle, and if said prefetch cache memory is determined not to contain said current line, then continuing said main memory cycle to retrieve said current line from said main memory and providing said current line to said processor, and further continuing said main memory cycle to retrieve said current line+1 from said main memory and storing said current line+1 in said prefetch cache memory. - View Dependent Claims (39)
-
Specification