Method and apparatus for firmware upgrades in embedded systems

• US 5,566,335 A
• Filed: 03/16/1993
• Issued: 10/15/1996
• Est. Priority Date: 03/16/1993
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Nash, Mark, Jedrzejewski, Mark
• Primary Examiner(s): Kriess, Kevin A.
• Application Number:
  US08/031,733
• Time in Patent Office: 1,309 Days
• Field of Search: 395/700, 395/650
• US Class Current: 713/1
• CPC Class Codes: G06F 8/66 of program code stored in read-only memory [ROM]
• CPC Class Codes: G06F 9/24 Loading of the microprogram

Abstract

Firmware updates for embedded systems are accomplished by using PROM in favor of conventional ROM, dividing the PROM into pages zero, one, two, etc., that can each contain an entire version of the embedded system. Pages of PROM are addressable by MSB address bits that originate from a circuit that selects page zero upon power-up, and that is responsive to a command in the firmware of the embedded system to increment the value of the MSB address bits. Upon initial fabrication, a product containing the embedded system has entirely unprogrammed PROM. An initial embedded system is zapped into page zero when the product is tested after being turned on for the first time. Replacement versions can be zapped into successive pages as the need arises. Each version includes an initialization routine and its own Get Next Page (GNP) bit. If a version is superseded by another, the old version indicates this by a GNP bit that gets programmed on the old page at the same time the replacement version is zapped into the new page. When that GNP bit is checked by its initialization routine the page selecting MSB address bits are incremented and the micro-processor executing the embedded system is reset; it now runs the initialization routine of the replacement version on the next page, which if not itself replaced, eventually branches out of the initialization routine to the main code of the replacement embedded system.

Claims

1. Apparatus for executing a more recently installed version of an embedded firmware system, the apparatus comprising:

processor means for executing embedded firmware system code and responsive to a processor reset signal by commencing execution from a start address;

memory means addressable by contiguous least significant bits defining an address space and originating at the processor means and also addressable by a most significant bit, the address space defined by the least significant bits being within one of first and second pages and the most significant bit determining which of the first and second pages is addressed by the least significant bits, the memory means for storing within the first page an initial version of the embedded firmware system and for storing within the second page a more recent version of the embedded firmware system;

the initial and more recent versions of the embedded firmware system each including respective initialization routines beginning at the start address within the page determined by the most significant bit;

the initial version of the embedded firmware system including an addressable flag location therein whose stored content indicates the presence or absence within the second page of the more recent version of the embedded firmware system;

register means for storing, setting and resetting the value of a page selection bit, the register means having an output coupled to the memory means as the most significant bit, and also having set and reset inputs for respectively setting and resetting the value of the page selection bit;

means for generating a power-up signal indicative of an application of power to the apparatus;

means, coupled to the power-up signal and to the reset input of the register means, for resetting the value of the page selection bit upon an application of power to the apparatus;

the initialization routine of the initial version of the embedded firmware system including a determination of the value of the flag location subsequent to which no setting of the page selection bit occurs if the flag location indicates that no more recent version of the embedded firmware system exists within the second page, and subsequent to which a setting of the page selection bit does occur if the flag location does so indicate; and

means coupled to the register means and to the power-up signal for issuing the processor reset signal upon either an instance of the power-up signal or a setting of the page selection bit.

2. Apparatus as in claim 1 wherein the initialization routine of the more recent version of the embedded firmware system includes a determination of the value of the page selection bit, made prior to the determination of the flag location, subsequent to which prior determination the page selection bit is left unaltered, no processor reset signal is issued, and the more recent version of the embedded firmware system is commenced by its initialization routine, if the prior determination is that the page selection bit is set.

3. Apparatus as in claim 1 wherein the memory means comprises programmable read only memories.

4. Apparatus for executing a most recently installed version of an embedded firmware system, the apparatus comprising:

processor means for executing embedded firmware system code and responsive to a processor reset signal by commencing execution from a start address;

memory means addressable by contiguous least significant bits defining an address space and originating at the processor means and also addressable by contiguous most significant bits, the address space defined by the least significant bits being within one of a plurality of pages and the most significant bits determining which page of the plurality of pages is addressed by the least significant bits, the memory means for storing within a first page an initial version of the embedded firmware system and for storing within second and subsequent pages respectively more recent versions of the embedded firmware system, the first page corresponding to an initial pattern of most significant bits and the second and subsequent pages corresponding respectively to successive increments of the initial pattern of most significant bits;

the initial, second and more recent versions of the embedded firmware system each including respective initialization routines beginning at the start address within the page determined by the most significant bits, and each also including an addressable flag location whose stored content indicates the presence or absence within the following page of a more recent version of the embedded firmware system;

register means for storing, incrementing and resetting a page selection pattern, the register means having an output coupled to the memory means as the most significant bits, and also having increment and reset inputs for respectively incrementing and resetting to the initial pattern thereof the page selection pattern;

means for generating a power-up signal indicative of an application of power to the apparatus;

means, coupled to the power-up signal and to the reset input of the register means, for resetting the value of the page selection pattern upon an application of power to the apparatus;

each version of the embedded firmware system including a determination of the value of its flag location subsequent to which no incrementing of the page selection pattern occurs if that flag location indicates that no more recent version of the embedded firmware system exists within a following page and subsequent to which an increment of the page selection pattern does occur if that flag location does so indicate; and

means coupled to the register means and to the power-up signal for issuing the processor reset signal upon either an instance of the power-up signal or a increment of the page selection pattern.

5. A method of revising an apparatus'"'"' embedded system whose code is fetched from PROM and executed by a processor, the method comprising the steps of:

a. addressing the PROM as an ordered series of pages, each page corresponding to the address space of the processor, and page selection accomplished by one or more address bits that originate from a page selection circuit and that are more significant than those from the processor;

b. storing an initial version of the embedded system in the first page of the ordered series thereof, the initial version including within its page an initialization routine whose starting address is that at which the processor begins execution subsequent to a reset applied to the processor and also including within its page a logical value of CLEAR in a revision flag whose meaning when having a logical value of SET, is that a revised version of the embedded system exists in the next page in the ordered series thereof;

c. causing, upon the application of power to the apparatus, the page selection circuit to select the first page in the ordered series thereof;

d. issuing, upon the application of power to the apparatus, a reset signal to the processor, causing the processor to begin executing the initialization routine of the initial version;

e. interrogating, as part of the initialization routine being executed, the revision flag included within the page presently selected by the page selection circuit;

f. if the revision flag interrogated in step (e) has a logical value of CLEAR, then executing the embedded system stored on the page presently selected by the page selection circuit; and

g. if the revision flag interrogated in step (e) has a logical value of SET, then;

h. incrementing the pattern of the more significant address bits that originate from the page selection circuit; and

then

i. issuing a reset signal to the processor, whereby steps (e) through (g) are repeated.

6. A method as in claim 5 further comprising the steps of:

j. storing a revised version of the embedded system within the first unused page in the ordered series of pages, the revised version including within its page an initialization routine whose starting address is that at which the processor begins execution subsequent to a reset applied to the processor and also including within its page a logical value of CLEAR in a revision flag whose meaning, when having a logical value of SET, is that a revised version of the embedded system exists in the next page in the ordered series of pages; and

k. setting the logical value of the revision flag in the page preceding that first unused page to SET.

8. A method as in claim 5 further comprising the steps of:

k. storing a revised version of the embedded system within the unused page in the ordered series of pages corresponding to stored page number, the revised version including within its page an initialization routine whose starting address is that at which the processor begins execution subsequent to a reset applied to the processor and also including within its page a logical value of CLEAR in a revision flag whose meaning when having a logical value of SET is that a revised version of the embedded system exists in the next page in the ordered series of pages, and additionally including within its page a stored page number identifying which page in the ordered series thereof is to contain a further revised version of the embedded firmware system; and

l. setting the logical value of the revision flag in the page preceding that first unused page to SET.

7. A method of revising an apparatus'"'"' embedded system whose code is fetched from PROM and executed by a processor, the method comprising the steps of:

a. addressing the PROM as an ordered series of pages, each page corresponding to the address space of the processor, and page selection accomplished by one or more address bits that originate from a page selection circuit and that are more significant than those from the processor;

b. storing an initial version of the embedded system in the first page of the ordered series thereof, the initial version including within its page an initialization routine whose starting address is that at which the processor begins execution subsequent to a reset applied to the processor and also including within its page a logical value of CLEAR in a revision flag whose meaning when having a logical value of SET is that a revised version of the embedded system exists in the next page in the ordered series thereof, and additionally including within its page a stored page number identifying which page in the ordered series thereof will contain a revised version of the embedded firmware system that is to be executed in place of the initial version;

c. causing, upon the application of power to the apparatus, the page selection circuit to select the first page in the ordered series thereof;

d. issuing, upon the application of power to the apparatus, a reset signal to the processor, causing the processor to begin executing the initialization routine of the initial version;

e. interrogating, as part of the initialization routine being executed, the revision flag included within the page presently selected by the page selection circuit;

f. if the revision flag interrogated in step (e) has a logical value of CLEAR, then executing the embedded system stored on the page presently selected by the page selection circuit; and

g. if the revision flag interrogated in step (e) has a logical value of SET, then;

h. reading the stored page number;

i. setting the pattern of the more significant address bits that originate from the page selection circuit to be the same as the stored page number read in step (i); and

then

j. issuing a reset signal to the processor, whereby steps (e) through (g) are repeated.

9. A method as in claim 7 wherein within each page the revision flag and the stored page number are stored in the same location and further comprising the step of indicating a logical value of CLEAR for the revision flag by the presence of an unprogrammed value in that same location and a logical value of SET with any programmed value that also identifies a page number.