Complementary concurrent cooperative multi-processing multi-tasking processing system using shared memories with a minimum of four complementary processors

• US 5,566,349 A
• Filed: 05/16/1994
• Issued: 10/15/1996
• Est. Priority Date: 05/16/1994
• Status: Expired due to Fees

• Current Assignee: Optimized Applications & Solutions Information Systems
• Original Assignee: Complementary Processing, Inc.
• Inventors: Trout, Ray C.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): PERVEEN, REHANA
• Application Number:
  US08/243,174
• Time in Patent Office: 883 Days
• Field of Search: 395/821, 395/840, 395/800, 395/841, 395/827, 395/475, 364/243, 364/245.5, 364/245.6, 364/245.7, 364/245.9
• US Class Current: 710/20
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Abstract

The system concept of the C3M2 System is to have the capability of providing a Processor for each major processing step of automated data processing, i.e. if you have four steps then you need a minimum of four but it could be 8 or 12 or 16 processors. The four major complementary functions encompass the four major functions of data processing (Input/Output, Data Computation, Storage and User I/F). The system shall be Multi-tasking for each step. Source headers, link lists and entity or object identifiers are the methods that shall be used for identity of the different classes, types and objects for the variety of data in the system. The source and data type are contained in the source header. The class and type identity are contained in the object identifiers. The multi-tasking would be by schedule (interleaved by priority). This was selected instead of cycle sharing for improved concurrency.

Claims

1. A computer system comprising

four processors, four memories, and a set of instructions for each processor, wherein the four processors comprise

an IO processor for receiving data inputs and processing said data inputs to provide data outputs;

a DP processor for performing a data processing function;

a DM processor for performing a data distribution function; and

a DS processor for performing a data storage function;

wherein the four memories comprise

at least one memory means for storing data from the IO processor;

a dedicated DP memory for storing data from the DP processor;

a dedicated DM memory for storing data from the DM processor; and

a dedicated DS memory for storing data from the DS processor;

and wherein the set of instructions for each processor comprises

IO instructions and means for causing the IO processor to transfer data outputs to the at least one memory means for storage;

DP instructions and means for causing the DP processor to retrieve dam from the at least one memory, process said data to form calculated data; and

to transfer the calculated data to the DP memory for storage;

DM instructions and means for causing the DM processor to retrieve data from the DS memory and to transfer the data retrieved to the DM memory for storage; and

DS instructions and means for causing the DS processor to retrieve data from at least one of the memory means for storing data from the IO processor and the DP memory and to transfer the retrieved data to the DS memory for storage.

2. A computer system as in claim 1 wherein the at least one memory means for storing data from the IO processor comprises

a DP cache memory operably associated with the DP processor;

and

a dedicated IO memory for storing data from the IO processor;

said computer system further comprising

IO instructions and means for causing the IO processor to transfer data outputs to the DP cache memory and to the dedicated IO memory;

wherein the DP instructions and means for causing the DP processor to retrieve data from a memory

causes the DP processor to retrieve data from the DP cache memory, and

the DS instructions and means for causing the DS processor to retrieve data from at least one of the memory means for storing data from the IO processor causes the DS processor to retrieve data from the dedicated IO memory.

3. A computer system as in claim 2 wherein

each data output from the IO processor is associated with a unique multicharacteristic identifier, and

the dedicated IO memory includes

a first memory portion for storing dynamic data;

a second memory portion for storing static data; and

a third memory portion for storing the multicharacteristic identifiers for the dynamic data and the static data.

4. A computer system as in claim 3 wherein the DS memory includes

a first memory portion for storing dynamic data, static data and calculated data grouped by a characteristic of the identifier associated with such data;

a second memory portion for storing the identifiers for the dynamic data, the static data and the calculated data; and

the DS instructions further cause the DS processor to reformat the retrieved data based on identifier characteristic and to transmit the reformatted data for storage in the DS memory.

5. A computer system as in claim 3 further comprising

a knowledgebase comprising

a KB processor and means for the KB processor to receive calculated data having a common identifier characteristic from the DP processor, perform a prediction function based on data trends for the data having the common identifier characteristic and produce a deviation signal when the calculated data from the DP processor is outside of predetermined limits from the value predicted by the KB processor;

a KB memory for storing response information appropriate for each of a plurality of deviation signals; and

instructions and means for causing the KB processor to retrieve the appropriate response information from the KB memory in response to the deviation signal and to transfer such response information to the DP processor.

6. A computer system as in claim 1 further comprising

an archive memory for storing data for archive from the DS processor;

instructions and means for causing the DS processor to retrieve data for archive from the first memory portion of the DS memory and the second memory portion of the DS memory and to transfer such data to the archive memory for storage.

7. A computer system as in claim 3 wherein

the multicharacteristic identifier includes an object number and a receipt time for each data input;

and

the DM instructions further cause the DM processor to reformat the retrieved data for the production of user notices, and to transfer the reformatted data to the DM memory for storage.

8. A computer system as in claim 1 further comprising

a user interface operably associated with the DM processor;

wherein the DM instructions include

a routine for determining whether a user notification should be transmitted to the user interface;

a routine for generating the user notification; and

a routine for transmitting the user notification from the DM processor to the user interface.

9. A computer system as in claim 1 further comprising

an external user interface operably associated with the IO processor;

wherein the IO instructions include

a routine for processing queries from the external user interface;

a routine for transmitting the processed queries from the external user interface to the DM processor;

a routine for processing query responses received from the DM processor; and

a routine for transmitting the processed query responses to the external user interface;

and wherein the DM instructions include

a routine for processing queries received from the IO processor;

a routine for retrieving data responsive to said query from the DM memory;

a routine for generating a query response based on the retrieved data; and

and a routine for transmitting the query response to the IO processor.

10. A computer system as in claim 3 wherein the IO instructions include a routine for assigning a processing priority designator to data inputs;

and a routine for scheduling the data inputs for ordered transmission to the DP processor in a priority scheduler having a cyclic unvarying predetermined priority designator sequence.

11. A computer system as in claim 10 wherein the computer system has a clock cycle speed and the sequence is selected based on said clock cycle speed so that the computer system has completed retrieval, processing and transmission to the DM memory of a first data sample having a common identifier characteristic prior to receipt by the IO processor of a second data sample having such common identifier characteristic.

12. A computer system as in claim 1 wherein

the IO instructions and means for causing the IO processor to transfer data to the IO memory for storage further comprises a routine for causing a flag to be placed with the transferred data;

and

the DP instructions and means for causing the DP processor to retrieve data from a memory and to transfer calculated data to the DP memory for storage further comprises a routine for removing the flag from the retrieved data and a routine for placing a flag with the transferred data.

13. A computer system as in claim 2 wherein

the DP instructions and means for causing the DP processor to retrieve data from the DP cache memory, process said data to form calculated data and to transfer the calculated data to the DP memory for storage further comprises a routine for transferring the calculated data to the DP cache memory for storage.

14. A computer system as in claim 13 wherein the DP instructions further comprise a routine for establishing a relationship between a most recently formed calculated data and a previously formed calculated data in the DP cache memory, generating a data value representative of such relationship, and transferring such value to the DP memory for storage.

15. A computer system as in claim 1 further comprising

a user interface operably associated with the DM processor;

wherein the DM instructions include

a routine for processing queries from the user interface;

a routine for retrieving data responsive to said query from the DM memory;

a routine for generating a query response based on the retrieved data; and

and a routine for transmitting the query response to the user interface.

16. A computer system as in claim 2 further comprising

an IO cache memory operably associated with the IO processor;

a data source operably associated with the IO cache memory, said data source transmitting object data and external I/F data to the IO cache memory for storage;

wherein the IO instructions include

a routine to retrieve object data from the IO cache memory;

a routine to retrieve external I/F data from the IO cache memory;

a routine for identifying the source, class and type of data formats and associated data parameters;

a routine to transfer the object data to the IO memory for storage; and

a routine to transmit queried data to external users.

17. A computer system as in claim 1 further comprising

an IO cache memory operably associated with the IO processor;

a DM cache memory operably associated with the DM processor;

an external user interface operably associated with the IO processor;

external user interface instructions and means for causing the external user interface to transmit queries to the IO cache memory for storage; and

a dedicated external user interface memory operably associated with the external user interface;

wherein the IO instructions include

a routine to retrieve queries from the IO cache memory;

a routine to format the queries in an appropriate protocol;

a routine to identify and transmit the queries to the DM cache memory for storage;

a routine to retrieve query responses from the DM cache memory;

a routine to format the query responses from the DM cache memory into the protocol;

a routine to transmit the queries and the query responses to the external user interface memory for storage.

18. A computer system as in claim 2 wherein

the DP instructions include

a routine for calculating a value for a predetermined relationship between data most recently retrieved from the DP cache memory and data previously retrieved from the DP cache memory;

a routine for transferring the value to the DP cache memory for storage;

a routine for calculating a calculated value trend from the stored values;

a routine for predicting a predicted value for the next retrieved data based on the trend from the stored values;

a routine for comparing the calculated value with the predicted value and completing further processing of the calculated value when the calculated value is outside of predetermined limits from the predicted value; and

a routine for transferring the calculated value from the DP cache memory to the DP memory for storage.

19. A computer system as in claim 1 further comprising

a DS cache memory operably associated with the DS processor;

an archive memory for storing data for archive from the DS processor;

wherein the DS instructions and means for causing the DS processor to retrieve data from IO memory causes the DS processor to retrieve such data into the DS cache memory;

wherein the DS instructions further include

a routine to retrieve dynamic data from the DS cache memory;

a routine to retrieve static data from the DS cache memory;

a routine to retrieve calculated data from the DS cache memory;

a routine to retrieve the identifiers for the dynamic data, the static data, and the calculated data from the DS cache memory;

a routine to convert the identifiers to record numbers;

a routine to convert the dynamic data, the static data, the calculated data and the record numbers to a relational data base format for storage as a relational data base;

a routine for storing the relational data base in the DS memory;

a routine for retrieving the relational data base from the DS memory;

a routine for storing the thus retrieved relational data base in the archive memory;

a routine for transferring the relational data base from the archive memory to an archive media for storage; and

a routine for transferring a relational data base from an archive media to the archive memory.

20. A computer system as in claim 1 further comprising:

a DM cache memory operably associated with the DM processor; and

a user interface operably associated with the DM processor;

and wherein the DM instructions include

a routine to retrieve data from the DS memory and to transfer the data retrieved to the DM cache memory for storage;

a routine to cause a flag to be placed with the data last retrieved from the DS memory;

a routine to transmit the data stored with the flag to the user interface;

a routine for determining whether a user notification should be transmitted to the user interface;

a routine for generating the user notification; and

a routine for transmitting the user notification from the DM processor to the user interface.

21. A computer system as in claim 1 further comprising:

a DM cache memory operably associated with the DM processor; and

a user interface operably associated with the DM processor;

at least one external database operably associated with the DM processor;

wherein the DM instructions include

a routine for processing queries received from the user interface;

a routine for identifying the external database containing data responsive to said query;

a routine for retrieving the data responsive to said query from the external database;

a routine for generating a query response based on the retrieved data; and

and a routine for transmitting the query response to the user interface.

22. A computer system as in claim 3 wherein

the IO instructions further include

a routine for causing the IO processor to assign a multicharacteristic identifier to each data input;

a routine for causing the IO processor to transmit the multicharacteristic identifier to the third memory portion of the IO memory.

23. A computer system as in claim 12 wherein

the DM instructions and means for causing the DM processor to retrieve data from the DS memory and to transfer the retrieved data to the DM memory further comprises a routine for removing the flag from the retrieved data and a routine for placing a flag with the transferred data;

and

the DS instructions and means for causing the DS processor to retrieve data from the IO memory and the DP memory and to transfer the retrieved data to the DS memory for storage further comprises a routine for removing the flag from the retrieved data and a routine for placing a flag with the transferred data.

24. A process for concurrently using four processors to cooperatively perform complementary data processing functions, said process comprising

receiving a data input in an IO processor;

processing the data input in the IO processor and producing an IO output;

transferring the IO output to an IO memory for storage;

transferring the IO output to a DP cache memory for storage;

retrieving an IO memory output from the IO memory;

receiving the retrieved IO memory output in a DS processor;

processing the received IO memory output in the DS processor and producing a DS output;

transferring the DS output to a DS memory for storage;

retrieving a DP cache memory output from the DP cache memory;

receiving the DP cache memory output in a DP processor;

processing the received DP cache memory output in the DP processor and producing a DP output;

transferring the DP output to the DP cache memory;

transferring the DP output to a DP memory for storage;

retrieving an DP memory output from the DP memory;

receiving the retrieved DP memory output in a DS processor;

processing the received DP memory output in the DS processor and producing a DS output;

transferring the DS output to the DS memory for storage;

retrieving a DS memory output from the DS memory;

receiving the retrieved DS memory output in a DM processor;

processing the received DS memory output in the DM processor and producing a DM output;

transferring the DM output to a DM memory for storage.

25. A process as in claim 24 further comprising

assigning a processing priority designator to data inputs to the IO processor;

and

scheduling the data outputs from the IO processor for ordered transmission to the DP processor in a priority scheduler having a cyclic unvarying predetermined priority designator sequence.

26. A process as in claim 24 further comprising

causing a flag to be placed with the IO output transferred to the IO memory for storage;

causing a flag to be placed with the IO output transferred to the DP cache memory for storage;

causing a flag to be placed with the DP output transferred to the DP memory for storage;

causing a flag to be placed with the DS output transferred to the DS memory for storage; and

causing a flag to be placed with the DM output transferred to the DM memory for storage.

27. A process as in claim 24 further comprising:

calculating a value for a predetermined relationship between data most recently retrieved from the DP cache memory and data previously retrieved from the DP cache memory;

transferring the value to the DP cache memory for storage;

calculating a calculated value trend from the stored values;

predicting a predicted value for the next retrieved data from the DP cache memory based on the trend from the stored values;

comparing the calculated value with the predicted value and completing further processing of the calculated value when the calculated value is outside of predetermined limits from the predicted value; and

transferring the calculated value from the DP cache memory to the DP memory for storage.

28. A process as in claim 24 further comprising:

processing a query from a user interface;

retrieving DM memory output responsive to said query from the DM memory;

generating a query response based on the retrieved DM memory output in the DM processor; and

transmitting the query response to the user interface.

29. A process as in claim 24 further comprising

assigning a unique multicharacteristic identifier to each data input to the IO processor;

transferring the multicharacteristic identifier as IO output to the IO memory for storage; and

transferring the multicharacteristic identifier as IO output to the DP cache memory for storage.

30. A process as in claim 24 further comprising

identifying dynamic data in the IO processor;

identifying static data in the IO processor;

transferring the dynamic data as IO output to a first portion of the IO memory for storage;

transferring the static data as IO output to a second portion of the IO memory for storage; and

transferring the multicharacteristic identifiers as IO output to a third portion of the IO memory for storage.

31. A process as in claim 30 further comprising

retrieving an IO memory output from the first portion of the IO memory;

retrieving an IO memory output from the second portion of the IO memory;

retrieving an IO memory output from the third portion of the IO memory;

receiving the retrieved IO memory outputs in the DS processor;

reformatting the received IO memory outputs in the DS processor and producing a reformatted DS output; and

transferring the reformatted DS output to the DS memory for storage.

32. A process as in claim 24 further comprising

determining in the DM processor whether a user notification should be transmitted to a user interface;

generating the user notification; and

transmitting the user notification from the DM processor to the user interface.