Register-read acknowledgment and prioritization for integration with a hardware-based interrupt acknowledgment mechanism

• US 5,566,352 A
• Filed: 01/04/1993
• Issued: 10/15/1996
• Est. Priority Date: 01/04/1993
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Wishneusky, John
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): PERVEEN, REHANA
• Application Number:
  US08/000,774
• Time in Patent Office: 1,380 Days
• Field of Search: 395/275, 395/725, 395/250, 395/200.06, 395/200.16, 395/309, 395/310, 395/478, 395/733, 395/868, 364/705
• US Class Current: 710/48
• CPC Class Codes: G06F 13/26 with priority control

Abstract

A register-based computer architecture is particularly suited for using a common resource, such as a host processor or CPU, to respond to multiple devices such as co-processors, slave processors, or peripherals via service requests initiated by these devices. The invention'"'"'s register acknowledgment and service prioritizing features are preferably added to, and integrated with, a prior-art, hardware-based interrupt acknowledgment mechanism, thus providing enhanced flexibility and performance. This architecture includes features for enhancing the support of a service-request based or queue-driven interface between the host processor and the supported devices, including a Service Request Status Register, a Service Request Configuration Register, and Service Request Acknowledge Register(s). From the point of view of the host processor, these registers are accessed as normal input/output read/write operations. From the point of view of the supported devices, such register operations appear to be interrupt acknowledgment operations. This transformation is effected by special-purpose logic within the architecture. The invention is preferably embodied in a monolithic integrated circuit that supports control by the host processor of a potentially large number of data communications ports. These features can be incorporated in pin compatible new versions of existing devices so as to be backwards compatible with the existing devices, thus allowing end users to gracefully upgrade their systems with minimal effort.

Claims

1. A computer system, comprising:

(a) a peripheral device operable to initiate a service request of one of a plurality of types of service requests by generating a service request signal;

(b) a service request controller, coupled to said peripheral device, having a register corresponding to a register address, and operable to receive said service request signal and to generate an interrupt request signal in response thereto; and

(c) a processor, coupled to said service request controller, operable, in response to said interrupt request signal, to interrupt its normal execution and to issue an interrupt acknowledgment, and having a read command operable to specify said register address thereby acknowledging a pending service request;

said service request controller being operable, in response to either said service request acknowledgment or said interrupt acknowledgment, to select which of the service requests currently pending is to be acknowledged based on which service request type has the highest priority, and to provide said processor with a vector corresponding to the service request being acknowledged.

2. A computer system according to claim 1 wherein said service request controller is operable to provide said processor with a predetermined vector in response to said read command specifying said register address when there is no service request pending.

3. A computer system according to claim 1, wherein

said service request controller has a plurality of registers corresponding to a plurality of register address and to said plurality of types of service requests;

and

said read command acknowledges service requests of a particular type by specifying said corresponding register address.

4. A computer system according to claim 1, wherein said types of service requests comprise transmit data service requests, receive data service requests, and modem signal change service requests.

5. A computer system according to claim 1, wherein

said service request controller has a control register operable to hold a current priority order among said types of service requests;

said service request controller performs said selection of which service request currently pending has the highest priority based on said current priority order; and

said processor can alter the value of said current priority order within said control register.

6. A computer system according to claim 1, wherein

said processor is operable in a normal mode to process information and in a service request mode to handle service requests;

and

after said processor completes handling a first service request and before said processor returns to said normal mode, said read command specifies said register address thereby acknowledging a second service request if one is pending.

7. A computer system, comprising:

(a) a plurality of peripheral devices, each operable to initiate a service request of one of a plurality of types of service requests by generating a corresponding service request signal;

(b) a plurality of service request controllers, each coupled to at least one of said peripheral devices, each having a register corresponding to a register address, and each operable to receive the service request signal corresponding to said coupled peripheral device and to generate an interrupt request signal in response thereto, said plurality of service request controllers being coupled together as a daisy chain with one of said service request controllers at the head of said daisy chain;

(c) a processor, coupled to said head service request controller, operable, in response to said interrupt request signal, to interrupt its normal execution and to issue an interrupt acknowledgment, and having a read command operable to specify said register address thereby providing a service request acknowledgment to said head service request controller;

each said service request controller being operable, in response to receipt of either said service request acknowledgment or said interrupt acknowledgment, to select one of the service requests pending from any of said peripheral devices connected thereto or, if there are no such pending service requests, to pass said service request acknowledgment on to the next service request controller in said daisy chain, said selecting or said passing being based on which service request type has the highest priority; and

each said service request controller being operable, in response to either said service request acknowledgment or said interrupt acknowledgment, to provide said processor with a vector that corresponds to the type of service request being acknowledged and that corresponds to which of said service controllers has said service request being acknowledged.

8. A computer system according to claim 7, wherein said service request controllers are operable to provide said processor with a predetermined vector in response to said read command specifying said register address when there is no service request pending.

9. A computer system according to claim 7, wherein

each said service request controller has a plurality of registers corresponding to a plurality of register address and to said plurality of types of service requests;

and

said read command acknowledges service requests of a particular type by specifying said corresponding register address.

10. A computer system according to claim 7, wherein said types of service requests comprise transmit data service requests, receive data service requests, and modem signal change service requests.

11. A computer system according to claim 7, wherein

said service request controller has a control register operable to hold a current priority order among said types of service requests;

said service request controller performs said selection of which service request currently pending has the highest priority based on said current priority order; and

said processor can alter the value of said current priority order within said control register.

12. A computer system according to claim 7, wherein said service request controllers are operable:

to select which of its currently pending service requests is to be acknowledged based on which has the highest priority when said read command acknowledges a predetermined type of service request and no other of said service request controllers has a higher priority service request pending; and

to pass the service request acknowledgment on to the next service request controller in said daisy chain when said read command acknowledges a predetermined type of service request and another of said service request controllers has a higher priority service request pending.

13. A computer system according to claim 7, wherein

each said service request controller has a control register operable to hold a current priority order among said basic types of service requests;

each said service request controller is operable to select said highest priority service request based on said current priority order; and

said processor can alter the value of said current priority order within each said control register.

14. A computer system according to claim 7, wherein

said processor is operable in a normal mode to process information and in a service request mode to handle service requests;

and

after said processor completes handling a first service request and before said processor returns to said normal mode, said read command acknowledges a second service request if one is pending.

15. A computer system, comprising:

(a) a first peripheral device operable to initiate a service request of one of a plurality of types of service requests by generating a service request signal;

(b) a service request controller, coupled to said first peripheral device, having a register corresponding to a register address, and operable to receive said service request signal and to generate a first interrupt request line signal in response thereto;

(c) a second peripheral device operable to initiate an interrupt by generating a second interrupt request line signal;

(d) an interrupt controller, coupled to said service request controller and to said second peripheral device, operable to generate a master interrupt request signal responsive to either said first or said second interrupt request line signals;

(e) a main memory to hold data corresponding to memory addresses; and

(f) a processor, coupled to said main memory, to said service request controller and to said interrupt controller, operable, in response to said interrupt request signal, to interrupt its normal execution and to issue an interrupt acknowledgment, and having a read command operable to specify a memory address thereby reading the data corresponding thereto from said main memory, said read command being further operable to specify said register address thereby acknowledging said service request;

said service request controller being operable, in response to either said service request acknowledgment or said interrupt acknowledgment, to select which of the service requests currently pending is to be acknowledged based on which service request type has the highest priority, and to provide said processor with a vector corresponding to the service request being acknowledged.

16. A computer system according to claim 15, wherein said service request controller is operable to provide said processor with a predetermined vector in response to said read command specifying said register address when there is no service request pending.

17. A computer system according to claim 15, wherein

said service request controller has a plurality of registers corresponding to a plurality of register address and to said plurality of types of service requests;

and

said read command acknowledges service requests of a particular type by specifying said corresponding register address.

18. A computer system according to claim 15, wherein said types of service requests comprise transmit data service requests, receive data service requests, and modem signal change service requests.

19. A computer system according to claim 15, wherein

said service request controller has a control register operable to hold a current priority order among said types of service requests;

said service request controller performs said selection of which service request currently pending has the highest priority based on said current priority order; and

said processor can alter the value of said current priority order within said control register.

20. A computer system according to claim 15, wherein

said processor is operable in a normal mode to process information and in a service request mode to handle service requests;

and

after said processor completes handling a first service request and before said processor returns to said normal mode, said read command specifies said register address thereby acknowledging a second service request if one is pending.

21. A service request controller operable in conjunction with a processor, comprising:

a register acknowledge recognition element, coupled to said processor, operable to recognize a register read acknowledgment from said processor;

an interrupt acknowledge recognition element, coupled to said processor, operable to recognize an interrupt acknowledgment from said processor;

a service acknowledgment prioritization element, coupled to said register acknowledge recognition element and to said interrupt acknowledge recognition element, operable, in response to recognition of either said register read acknowledgment or of said interrupt acknowledgment, to select which of any pending service requests is to be acknowledged, and operable, when said read command specifies a predetermined register address, to select which of the service requests currently pending is to be acknowledged based on which has the highest priority; and

a modified service vector element, coupled to said service acknowledgment prioritization element, operable to receive therefrom an indication of said acknowledged service request and to provide said processor with a modified service vector corresponding thereto.

22. A computer system according to claim 21, wherein said modified service vector element is operable to provide said processor with a predetermined vector in response to said processor issuing a register read acknowledgment when there is no service request pending.

23. A computer system according to claim 21, wherein

said register acknowledge recognition element has a plurality of registers corresponding to a plurality of register address and to a plurality of types of service requests;

and

said processor acknowledges service requests of a particular basic type by specifying said corresponding register address.

24. A computer system according to claim 21, wherein said basic types of service requests comprise transmit data service requests, receive data service requests, and modem signal change service requests.

25. A computer system according to claim 21, wherein said service request controller further comprises:

a control register operable to hold a current priority order among said types of service requests; and

said service acknowledgment prioritization element is operable, when said processor specifies a predetermined register address, to select which of the service requests currently pending is to be acknowledged based on which has the highest priority based on said current priority order, said processor being able to alter the value of said current priority order within said control register.