Method for inspecting a semiconductor device

• US 5,566,877 A
• Filed: 05/01/1995
• Issued: 10/22/1996
• Est. Priority Date: 05/01/1995
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: McCormack, Dave W.
• Primary Examiner(s): Ramsey, Kenneth J.
• Application Number:
  US08/432,356
• Time in Patent Office: 540 Days
• Field of Search: 228/105, 228/103, 348/129, 348/130, 348/126
• US Class Current: 228/105
• CPC Class Codes: G01N 21/8803 Visual inspection measuring projectors G01B9/08
• CPC Class Codes: H01L 2224/859 involving monitoring, e.g. feedback loop

Abstract

A method for inspecting a semiconductor device includes an inspection station (10), a handling system (12), a microscope (14), a camera (18), and a computer (20) having a monitor (22). A magnified image (40) of the device being inspected is transmitted to monitor (22) via camera (18). A template image (60) is then recalled from computer readable memory and is superimposed upon the magnified image of the device appearing on monitor (22). The template image (60) includes transparent regions (62) and opaque regions (64). The opaque regions block out all areas of the device not associated with the characteristic being inspected, while the transparent regions highlight the area of interest. Using the superimposed image (70), the operator can quickly focus on the area of the device requiring attention. In specific embodiments of the invention, a template is used to assist inspection of a wire bond configuration, a die attach material bondline, lead skew, and mark placement.

Claims

1. A method for inspecting a semiconductor device comprising the steps of:

providing a semiconductor device having a characteristic to be inspected;

providing an inspection station having a magnification lens, a monitor, and a camera coupled to the magnification lens and the monitor for transmitting magnified images created by the magnification lens to the monitor;

creating a template which represents an acceptable range of values for the characteristic;

storing the template in a computer readable memory;

placing the semiconductor device under the magnification lens;

displaying a magnified image of the semiconductor device on the monitor using the camera;

retrieving the template from the computer readable memory;

displaying an image of the template on the monitor, superimposed with the magnified image of the semiconductor device; and

comparing the magnified image of the semiconductor device with the template to see if the characteristic of the semiconductor device falls within the acceptable range of values.

2. The method of claim 1 wherein the step of providing a semiconductor device comprises providing a semiconductor device having a die attach material bondline as the characteristic to be inspected.

3. The method of claim 2 wherein the step of displaying an image of the template comprises displaying at least two opaque lines that together define a lower limit and an upper limit for an acceptable location of the die attach material bondline along a side face of a semiconductor die.

4. The method of claim 1 wherein the step of providing a semiconductor device comprises providing a semiconductor device having a wire bond configuration as the characteristic to be inspected.

5. The method of claim 4 wherein the step of displaying an image of the template comprises displaying an image of a template which is transparent in regions corresponding to wire bonded areas and is opaque in other areas.

6. The method of claim 1 wherein the step of creating a template comprises creating a template having alpha-numeric notations to aid in the step of comparing.

7. The method of claim 1 wherein the step of providing a semiconductor device comprises providing a packaged semiconductor device having a plurality of leads, wherein the characteristic to be inspected is a location of each lead of the plurality of leads.

8. The method of claim 7 wherein the step of displaying an image of the template comprises displaying a transparent polygon corresponding in location within the template to an acceptable location for a lead to be inspected.

9. A method for inspecting a semiconductor device comprising the steps of:

providing an semiconductor die having a plurality of wire bonds;

providing a computer having a memory and having a monitor;

providing an inspection station having a handling system for moving the semiconductor die, a microscope for viewing the semiconductor die, and a camera coupled to the microscope and the monitor to portray a magnified image of the semiconductor die on the monitor;

using the handler to position the semiconductor die in a field of view of the microscope;

displaying the magnified image of the semiconductor die on the monitor;

retrieving a template of a wire bond configuration from the memory of the computer;

displaying an image of the template on the monitor, superimposed on the magnified image of the emiconductor die; and

comparing the semiconductor die and the plurality of wire bonds to the template to see if the semiconductor die is properly wire bonded.

10. The method of claim 9 wherein the step of displaying an image of the template comprises displaying the image such that the image includes a graphical symbol indicating a desired wire bond count for a segment of the semiconductor die.

11. The method of claim 9 wherein the step of displaying a magnified image of the semiconductor die comprises displaying a magnified image of an entirety of a top surface of the semiconductor die.

12. The method of claim 9 wherein the step of displaying an image of the template comprises displaying the image such that the image is transparent in areas associated with the plurality of wire bonds and is opaque in other areas.

13. The method of claim 12 further comprising the step of toggling displays on the monitor between the magnified image of the semiconductor die and the image of the template superimposed on the magnified image of the semiconductor die to look for wire bonds which may be hidden by opaque areas of the image of the template.

14. A method of inspecting a semiconductor device comprising the steps of:

providing a semiconductor die having a plurality of bond pads formed on a surface;

providing a plurality of leads and a die flag;

mounting the semiconductor die to the die flag;

wire bonding a plurality of wire bonds between the plurality of bond pads and the plurality of leads to create a wire bonded die; and

inspecting the plurality of wire bonds for accuracy of configuration, wherein the step of inspecting comprises the steps of;

positioning the wire bonded die on a stage within a field of view of a microscope;

transmitting a magnified image of the wire bonded die from the microscope to a monitor using a camera;

retrieving a template file from a computer readable memory;

using the template file to display an image of a wire bond template on the monitor superimposed onto the magnified image of the wire bonded die, wherein the image of the wire bond template has a transparent region outlining an area of the wire bonded die which is supposed to include at least one wire bond, and wherein the magnified image of the wire bonded die is visible on the monitor within the transparent region.

15. The method of claim 14 wherein the step of positioning comprises positioning the wire bonded die such that an entirety of the surface is within the field of view of the microscope.

16. The method of claim 14 wherein the step of using the template file comprises using the template file to display an image of a wire bond template, wherein the wire bond template has an opaque region corresponding to a region of the wire bonded die which is supposed to be void of any wire bonds, and wherein the magnified image of the wire bonded die cannot be seen on the monitor within the opaque region.

17. The method of claim 14 wherein the step of using the template file comprises using the template file to display an image of a wire bond template which includes alpha-numeric symbols for aiding in the step of inspecting.

18. A method for inspecting a semiconductor device comprising the steps of:

providing a semiconductor die having a plurality of sides, each side having a height;

providing a substrate;

mounting the semiconductor die to the substrate using a die attach material, wherein the step of mounting creates a die attach material bondline along each side of the semiconductor die; and

inspecting a location of the die attach material bondline,

wherein the step of inspecting comprises the steps of;

positioning one side of the semiconductor die within a field of view of a microscope;

transmitting a magnified image of the one side from the microscope to a monitor;

retrieving a template file from a computer readable memory; and

using the template file to display an image of a bondline template on the monitor, superimposed onto the magnified image of the one side of the semiconductor die, wherein the image of the bondline template has a transparent region appoximately corresponding in position and size to the one side as magnified and has a first opaque line corresponding to an acceptable location of the die attach material bondline, and wherein the magnified image of the one side is visible on the monitor within the transparent region.

19. The method of claim 18 wherein the step of using the termplate file comprises using the template file to display an image of a bondline template, wherein the image of the bondline template has a second opaque line, wherein the first opaque line corresponds to a maximum acceptable location of the die attach material bondline, and wherein the second opaque line corresponds to a minimum acceptable location of the die attach material bondline.

20. A method for inspecting a semiconductor device comprising the steps of:

providing a packaged semiconductor device having a plurality of external leads; and

inspecting a position of each lead of the plurality of external leads, the step of inspecting comprising the steps of;

positioning the packaged semiconductor device within a field of view of a microscope such that all leads of the plurality of external leads are visible within the field of view;

transmitting a magnified image of the packaged semiconductor device from the microscope to a monitor;

retrieving a template file from a computer readable memory;

generating a template image from the template file, wherein the template image includes a transparent region defining a boundary of an acceptable, lead location; and

displaying the template image on the monitor, superimposed on the magnified image of the packaged semiconductor device such that at least one lead is visible on the monitor through the transparent region.

21. The method of claim 20 wherein the step of generating a template image comprises generating a template image having a plurality of transparent regions, wherein each lead of the plurality of external leads has a corresponding transparent region.

22. The method of claim 21 wherein each transparent region of the plurality of transparent regions has a quadrangle shape.