Method of fabricating self-aligned contact trench DMOS transistors

• US 5,567,634 A
• Filed: 05/01/1995
• Issued: 10/22/1996
• Est. Priority Date: 05/01/1995
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Hebert, Francois, Bencuya, Izak, Kwan, Sze-Hon
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/431,765
• Time in Patent Office: 540 Days
• Field of Search: 437/40 DM, 437/41 DM, 437/203, 257/330, 257/332, 257/333
• US Class Current: 438/270
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of fabricating a trench DMOS transistor structure results in the contact to the transistor'"'"'s source and body being self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low on-resistance and higher current drive capability. The process flow maximizes the height of the trench poly gate prior to formation of oxide spacers for the self-contact contact, thereby ensuring sufficient step height for the spacers.

Claims

1. A method of fabricating a trench DMOS transistor structure having a source and a body and a contact to the source and body of the transistor structure that is self-aligned to a trench formed to isolate the transistor structure, the method comprising:

forming a silicon dioxide layer on an underlying layer of N-type epitaxial silicon;

forming a nitride layer on the silicon dioxide layer, the nitride layer having an upper surface;

forming a low temperature oxide (LTO) layer on the nitride layer to define an LTO/nitride/silicon dioxide (ONO) sandwich;

defining a trench mask on the LTO layer to expose regions of the LTO layer;

etching the ONO sandwich to expose regions of the N-type epitaxial layer underlying the exposed regions of the LTO layer;

etching the exposed regions of the N-type epitaxial layer to define trenches therein;

forming silicon dioxide on exposed surfaces of the trenches;

depositing a polysilicon layer to fill the trenches;

etching the polysilicon layer to define polysilicon gate regions within the trenches, each polysilicon gate region having an upper surface that is higher than the upper surface of said nitride layer;

removing the LTO layer;

removing the nitride layer;

implanting P-dopant to form a region of P-type conductivity between the trenches;

defining an N+ source mask and using the N+ source mask to implant N-dopant to define N+ source regions adjacent to the trenches;

oxidizing the polysilicon gate regions to form oxide pads on the upper surface of the polysilicon gate regions and oxide spacers on exposed sidewalls of the polysilicon gate regions such that the oxide spacers extend over the N+ source regions;

implanting P-dopant to form P+ body ohmic contact regions between the N+ source regions; and

forming a conductive layer over the oxide pads and the oxide spacers for contact with the P+ body ohmic contact regions.