Method of making a three dimensional trench EEPROM cell structure

• US 5,567,635 A
• Filed: 05/17/1994
• Issued: 10/22/1996
• Est. Priority Date: 03/23/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Acovic, Alexandre, Wu, Being S., Hsu, Ching-Hsiang
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/245,724
• Time in Patent Office: 889 Days
• Field of Search: 437/38, 437/43, 437/49, 437/67, 437/195, 437/915, 148/DIG. 50, 148/DIG. 164
• US Class Current: 438/259
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The objects of the present invention are accomplished by merging a MOS-FET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region of the transfer FET of the EEPROM cell. The heavily doped source and drain regions are formed on two vertical sidewalls of the trench and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench are formed by isolation oxide. A first silicon dioxide layer covers the bottom of the trench and forms part of the gate oxide of the cell device. A second silicon dioxide layer covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer. The second silicon dioxide layer separates the source and drain regions from the floating gate which overlays both the first and second silicon dioxide layers. The floating gate overlaps all four trench sidewalls and substantially increases the coupling between the floating-gate and the control-gate.

Claims

1. A method of making a semiconductor device, comprising:

etching a trench in a semiconductor substrate, said trench etching forming first and second trench sidewalls and a channel region, said channel region seperating said first trench sidewall from said second trench sidewall;

partially filling said trench with isolation material to form first and second isolation sidewalls in said trench, said channel region seperating said first isolation sidewall from said second isolation sidewall;

doping said first and second trench sidewalls with a first type of dopant;

forming a first dielectric layer over said first and second trench sidewalls;

forming a second dielectric layer over said channel region; and

forming a floating gate covering said second dielectric layer and at least partially covering said first dielectric layer, said floating gate having an interface side and a patterned side, said interface side contacting said first and second dielectric layers, said patterned side having at least two generally planar surfaces for increasing capacitance between said floating gate and said control gate.

2. A method for making a semiconductor device, as in claim 1, wherein:

said floating gate at least partially covers said first and second isolation sidewalls.

3. A method for making a semiconductor device, as in claim 1, wherein:

said first dielectric layer has a thickness less than said second dielectric layer; and

said first dielectric layer has a thickness of less than approximately 150 Å

.

4. A method for making a semiconductor device, as in claim 2, wherein:

said first dielectric layer has a thickness less than said second dielectric layer; and

said first dielectric layer has a thickness of less than approximately 150 Å

.

5. A method for making a semiconductor device, as in claim 3, wherein:

said first type of dopant is N-type.

6. A method for making a semiconductor device, as in claim 3, wherein:

said first type of dopant is P-type.

7. A method for making a semiconductor device, as in claim 4, wherein:

said first type of dopant in N-type.

8. A method for making a semiconductor device, as in claim 4, wherein:

said first type of dopant is P-type.

9. A method of making a semiconductor device, comprising:

etching a trench in a semiconductor substrate, said trench etching forming first and second trench sidewalls and a channel region, said channel region separating said first trench sidewall from said second trench sidewall;

partially filling said trench with isolation material to form first and second isolation sidewalls in said trench, said channel region separating said first isolation sidewall from said second isolation sidewall;

doping said first and second trench sidewalls with a first type of dopant;

forming a first dielectric layer over said first and second trench sidewalls;

forming a second dielectric layer over said channel region;

forming a floating gate covering said second dielectric layer and at least partially covering said first dielectric layer, said floating gate having an extension portion extending outside said trench; and

etching away said extension portion so that said floating gate is confined to said trench.

10. The method of claim 9 wherein said etching is performed by polishing.

11. The method of claim 10 wherein said polishing is chemical and mechanical polishing.