Method of fabricating gate electrode of CMOS device

• US 5,567,642 A
• Filed: 11/06/1995
• Issued: 10/22/1996
• Est. Priority Date: 11/08/1994
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Kim, Hyeon S., Lee, Choong H.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Pham, Long
• Application Number:
  US08/554,337
• Time in Patent Office: 351 Days
• Field of Search: 437/56, 437/34, 437/57, 437/58, 437/186, 437/200, 148/DIG. 19, 257/369, 257/371
• US Class Current: 438/232
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: Y10S 148/019 Contacts of silicides

Abstract

A method of fabricating a gate electrode of a CMOS device is disclosed including the steps of: sequentially forming a gate insulating layer, first conductive layer and protective layer on a semiconductor substrate; selectively etching a predetermined portion of the protective layer in which a PMOS transistor will be formed; forming a second conductive layer on the overall surface of said substrate; removing the second conductive layer formed on the protective layer, and partially etching the protective layer to a predetermined thickness; and patterning the second conductive layer, the protective layer, the first conductive layer and the gate insulating layer using a gate electrode pattern.

Claims

1. A method of fabricating a gate electrode of a CMOS device, comprising the steps of:

sequentially forming a gate insulating layer, a first conductive layer and a protective layer on a semiconductor substrate;

selectively etching a portion of said protective layer in which a PMOS transistor is formed;

forming a second conductive layer on a resulting surface of said substrate;

removing said second conductive layer formed on said protective layer, and partially etching said protective layer to a first thickness; and

patterning said second conductive layer, said protective layer, said first conductive layer and said gate insulating layer to form a gate electrode.

2. The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, wherein said first conductive layer is formed of polysilicon.

3. The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, wherein said second conductive layer is formed of silicide.

4. The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, after the step of selectively etching a portion of said protective layer, further comprising the step of:

partially etching an exposed portion of said first conductive layer to a second thickness.

5. The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, wherein said protective layer is partially removed to a first thickness so as to make surface heights of said protective layer and said second conductive layer same.

6. The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, after the step of partially etching said protective layer to a first determined thickness, further comprising the step of:

ion-implanting a V-group impurity and III-group impurity into NMOS and PMOS transistor regions, respectively.

7. The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, wherein said protective layer is formed thicker than said second conductive layer.

8. The method of fabricating a gate electrode of a CMOS device as claimed in claim 1, wherein said second conductive layer formed on said protective layer and said protective layer are removed using an etchant.