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Method of fabricating gate electrode of CMOS device

  • US 5,567,642 A
  • Filed: 11/06/1995
  • Issued: 10/22/1996
  • Est. Priority Date: 11/08/1994
  • Status: Expired due to Term
First Claim
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1. A method of fabricating a gate electrode of a CMOS device, comprising the steps of:

  • sequentially forming a gate insulating layer, a first conductive layer and a protective layer on a semiconductor substrate;

    selectively etching a portion of said protective layer in which a PMOS transistor is formed;

    forming a second conductive layer on a resulting surface of said substrate;

    removing said second conductive layer formed on said protective layer, and partially etching said protective layer to a first thickness; and

    patterning said second conductive layer, said protective layer, said first conductive layer and said gate insulating layer to form a gate electrode.

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