Process for aligning etch masks on an integrated circuit surface using electromagnetic energy

• US 5,567,653 A
• Filed: 09/14/1994
• Issued: 10/22/1996
• Est. Priority Date: 09/14/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Cronin, John E., Perlman, David J.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US08/306,042
• Time in Patent Office: 769 Days
• Field of Search: 437/208, 437/915, 437/974, 437/229, 437/984, 437/173, 437/228 M, 437/228 MRK, 437/924, 430/313, 430/327, 257/777, 257/797
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.

Claims

1. A method for aligning a pattern formed on a first surface of an integrated circuit chip with a complementary pattern formed on a second surface of said integrated circuit chip, said first surface having devices therebelow, said method comprising the steps of:

etching the pattern into said first surface according to a first mask aligned to said devices, said pattern having regions of different heights relative to said first surface;

irradiating said first surface with penetrating electromagnetic energy, the penetrating electromagnetic energy being affected by said pattern or said devices Upon passage through said chip;

aligning a second mask adjacent said second surface to said pattern including sensing said affected penetrating electromagnetic energy emanating from said second surface and aligning said second mask according to the sensed affected penetrating electromagnetic energy; and

etching a complementary pattern into said second surface according to said second mask, said complementary pattern having regions of different heights relative to said second surface.

2. The method of claim 1, further comprising the step of repeating all said steps for each of a plurality of integrated circuit chips such that upon stacking said plurality of integrated circuit chips the patterns and complementary patterns of adjacent ones of said plurality of integrated circuit chips will interlock.

3. The method of claim 2, further comprising the step of providing electrically conducting pads on corresponding edges of selected ones of said plurality of integrated circuit chips such that upon stacking said plurality of integrated circuit chips said electrically conducting pads are aligned on a module face formed from said corresponding edges.

4. The method of claim 3, further comprising forming an electrical wiring network on said module face, said electrical wiring network electrically contacting selected ones of said electrically conducting pads.

5. The method of claim 1, further comprising the steps of:

repeating all said steps for each of a plurality of integrated circuit chips; and

stacking said plurality of integrated circuit chips such that the patterns and complementary patterns of adjacent ones of said plurality of integrated circuit chips interlock.

6. The method of claim 5, further comprising the step of providing electrically conducting pads on corresponding edges of at least two of said plurality of integrated circuit chips such that upon stacking said plurality of integrated circuit chips said electrically conducting pads are aligned on a module face formed from said corresponding edges.

7. The method of claim 6, further comprising the step of forming an electrical wiring network on said module face, said electrical wiring network electrically contacting at least two of said electrically conducting pads.

8. The method of claim 1, wherein said pattern is etched into a first layer disposed on said first surface.

9. The method of claim 8, wherein said first layer comprises a thickness control layer.

10. The method of claim 1, wherein said complementary pattern is etched into a second layer disposed on said second surface.

11. The method of claim 10, wherein said second layer comprises a thickness control layer.