Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging

• US 5,567,654 A
• Filed: 09/28/1994
• Issued: 10/22/1996
• Est. Priority Date: 09/28/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Cronin, John E., Perlman, David J., Leas, James M., Howell, Wayne J., Beilstein, Kenneth E. Jr.
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/313,976
• Time in Patent Office: 755 Days
• Field of Search: 437/209, 437/208, 437/211, 437/212, 437/214, 437/215, 437/216, 437/217, 437/218, 437/219, 437/220, 437/974
• US Class Current: 438/4
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Claims

1. A method for establishing a thin-film layer on a semiconductor structure having a planar surface, said thin-film layer comprising a metallization layer, said semiconductor structure comprising a plurality of stacked integrated circuit (IC) chips having a plurality of edge surfaces that at least partially define said planar surface of said semiconductor structure, said method comprising the steps of:

(a) forming the metallization layer in association with a temporary support separate from the semiconductor structure;

(b) electrically coupling the metallization layer to the planar surface of the semiconductor structure such that said metallization layer physically bonds to said planar surface and said temporary support is coupled to said semiconductor structure, wherein said metallization layer electrically connects to said semiconductor structure; and

(c) decoupling the temporary support from said semiconductor structure, said metallization layer remaining electrically coupled and physically bonded to said planar surface of the semiconductor structure.

2. The method of claim 1, wherein said forming step (a) includes associating said thin-film layer with said temporary support via a temporary adhesive.

3. The method of claim 1, wherein said forming step (a) includes forming said thin-film layer on a first surface of a substrate, said substrate being coupled to said temporary support such that said thin-film layer is associated with said temporary support.

4. The method of claim 1, wherein said forming step (a) includes forming said thin-film layer on a first surface of a passive film, said passive film being coupled to said temporary support such that said thin-film layer is associated with said temporary support.

5. The method of claim 1, wherein said electrically coupling step (b) includes electrically coupling the metallization layer to the planar surface of the semiconductor structure such that said metallization layer electrically interconnects at least some of said plurality of stacked IC chips.

6. The method of claim 5, wherein said planar surface of said semiconductor structure has a plurality of balancing pads thereon, and wherein said electrically coupling step (b) includes mechanically bonding said metallization layer to said planar surface of said semiconductor structure such that said plurality of stacked integrated circuit chips is partially supported by said plurality of balancing pads.

7. The method of claim 5, wherein each integrated circuit chip of said plurality of stacked integrated circuit chips has a spacer disposed between itself and an adjacent integrated circuit chip of said plurality of stacked integrated circuit chips comprising said semiconductor structure, and wherein said planar surface of said semiconductor structure has a plurality of balancing pads thereon, said electrically coupling step (b) including mechanically bonding said metallization layer to said planar surface such that said plurality of stacked integrated circuit chips are partially supported by said plurality of balancing pads.

8. The method of claim 7, further comprising the step of removing said spacer after said electrical coupling step (b).

9. The method of claim 1, wherein said forming step (a) includes forming said thin-film layer to have a first plurality of electrical contacts for facilitating said electrically coupling step (b).

10. The method of claim 9, wherein said planar surface of said semiconductor structure has a second plurality of electrical contacts thereon, and wherein said electrically coupling step (b) includes electrically connecting at least some of said first plurality of electrical contacts to said second plurality of electrical contacts.

11. The method of claim 10, wherein said electrically coupling step (b) includes insulating a first electrical contact of said first plurality of electrical contacts from a first electrical contact of said second plurality of electrical contacts.

12. The method of claim 11, wherein said electrically coupling step (b) includes depositing an insulating layer over said first electrical contact of said first plurality of electrical contacts.

13. The method of claim 12, wherein said electrically coupling step (b) includes depositing a second electrical contact over said insulating layer.

14. The method of claim 11, wherein said electrically coupling step (b) includes depositing a plurality of solder bumps on said first plurality of electrical contacts and removing a solder bump from said first electrical contact of said first plurality of electrical contacts.

15. The method of claim 1, wherein said forming step (a) includes forming said thin-film layer as a metallization layer on a substrate having a first surface and a second surface such that said metallization layer is disposed on said first surface, said substrate including an active circuit layer disposed on said second surface, said substrate being coupled to said temporary support such that said metallization layer is associated with said temporary support, and wherein said electrically coupling step (b) further comprises electrically coupling said active circuit layer to the semiconductor structure.

16. The method of claim 15, wherein said forming step (a) includes providing said substrate with a plurality of electrically conductive vias that electrically connect said metallization layer and said active circuit layer.

17. The method of claim 15, wherein said forming step (a) includes forming said active circuit layer to have a plurality of electrical contacts for facilitating electrical contact thereof to a circuit external from said electronic module.

18. The method of claim 1, wherein said forming step (a) includes forming said thin-film layer as a first metallization layer on a passive film having a first surface and a second surface such that said first metallization layer is disposed on said first surface, said passive film including a second metallization layer disposed on said second surface and being coupled to said temporary support such that said first metallization layer is associated with said temporary support, and wherein said electrically coupling step (b) further comprises electrically coupling said second metallization layer to the semiconductor structure.

19. The method of claim 18, wherein said forming step (a) includes providing said passive film with a plurality of electrically conductive vias that electrically connect said first metallization layer and said second metallization layer.

20. The method of claim 18, wherein said forming step (a) includes forming said second metallization layer to have a plurality of electrical contacts for facilitating electrical contact to a circuit external from said electronic module.

21. The method of claim 1, wherein said planar surface of said plurality of stacked IC chips is free of interconnections between the plurality of stacked IC chips formed thereon, such that said plurality of stacked IC chips are not electrically connected to each other until said electrically coupling step (b).

22. A method for establishing a metallization layer on a side surface of an electronic module, said electronic module comprising a plurality of stacked integrated circuit chips having a plurality of edge surfaces that at least partially define the side surface of the electronic module, said method comprising the steps of:

(a) forming a metallization layer on a first surface of a substrate, said substrate having said first surface, a second surface, and a plurality of electrically conductive vias extending between said first surface and said second surface, said substrate further including an active circuit layer disposed on said second surface and a plurality of electrical contacts for facilitating electrical contact to a circuit external to said electronic module, said metallization layer and said active circuit layer being electrically connected by said plurality of electrically conductive vias;

(b) coupling said metallization layer to a temporary support via a temporary adhesive layer, wherein said steps (a) and (b) are performed physically independent from the electronic module;

(c) electrically coupling the metallization layer to the side surface of the electronic module such that said metallization layer mechanically bonds to said side surface and said temporary support is coupled to said electronic module, wherein said metallization layer at least partially interconnects said plurality of stacked integrated circuit chips comprising said electronic module; and

(d) detaching the temporary support from said electronic module along the temporary adhesive layer, wherein said metallization layer remains bonded to said side surface of the electronic module and said substrate and said active circuit layer having said plurality of electrical contacts remains coupled to said electronic module.

23. A method for forming an electronic package comprising the steps of:

(a) providing an electronic module comprising a plurality of stacked integrated circuit chips and having a planar side surface;

(b) providing an interposer comprising a first planar main surface and an active circuit layer; and

(c) electrically coupling said planar side surface of said electronic module to said first planar main surface of said interposer such that said active circuit layer functions in conjunction with the electronic module.

24. The method of claim 23, wherein said interposer includes an extending portion that extends beyond said side surface of said electronic module when coupled thereto, said method including encapsulating said electronic module, said encapsulating being performed to said extending portion of said interposer.

25. The method of claim 24, wherein said encapsulating of said electronic module comprises hermetically sealing said electronic module.

26. The method of claim 23, wherein said providing step (a) comprises firming said planar side surface without use of lithography steps.

27. The method of claim 23, further including the step of attaching a thermal management device to the electronic package.

28. A method for forming an electronic package comprising the steps of:

(a) providing an electronic module comprising a plurality of stacked integrated circuit chips, said electronic module having a planar surface;

(b) providing a cavity substrate having a cavity therein;

(c) providing an active integrated circuit chip; and

(d) mechanically coupling said active integrated circuit chip and said electronic module to said cavity substrate such that said electronic module and said active integrated circuit chip are recessed within said cavity and said active integrated circuit chip is disposed between said cavity substrate and said planar surface of said electronic module.

29. The method of claim 28, further including the step of thermally managing said electronic module.

30. The method of claim 28, further including the step of encapsulating the electronic package, for protecting said electronic package from a surrounding environment.

31. The method of claim 28, further including the steps of connecting a means for thermal management to said electronic module.

32. The method of claim 28, further including the step of electrically connecting the substrate and the active integrated circuit chip.

33. The method of claim 28, further including the step of electrically connecting the substrate and the electronic module.

34. The method of claim 28, wherein said substrate includes a plurality of wirebond pads disposed on a plurality of wirebond pad levels, said method further including the step of electrically attaching said wirebond pads to at least one of said active integrated circuit chip and said electronic module.

35. The method of claim 28, further including the step of depositing a thin-film metallization layer between said electronic module and said active integrated circuit chip for electrically interconnecting at least some of the plurality of stacked integrated circuit chips.

36. A method for forming an electronic package comprising the steps of:

(a) providing a cavity substrate having a cavity therein;

(b) providing a first semiconductor structure within said cavity and providing a second semiconductor structure;

(c) mechanically coupling said cavity substrate, said first semiconductor structure and said second semiconductor structure such that said cavity substrate and said first semiconductor structure comprise a planar surface to which said second semiconductor structure is coupled.

37. The method of claim 36, further including the step of thermally managing said electronic package.

38. The method of claim 36, further including the step of electrically attaching said first semiconductor structure and said substrate.

39. The method of claim 36, further including the step of electrically attaching said second semiconductor structure and said substrate.

40. The method of claim 36, wherein said second semiconductor structure includes a first portion and a second portion coplanar with said first portion, said method further including the steps of:

electrically attaching and mechanically bonding said first portion of said second semiconductor structure to said substrate, and electrically attaching and mechanically bonding said second portion of said second semiconductor structure to said first semiconductor structure.

41. A method for forming an electronic package comprising the steps of:

(a) providing an electronic module comprising a plurality of stacked integrated circuit chips, said electronic module having a planar surface;

(b) providing a cavity substrate having both a cavity and an opening therein; and

(c) mechanically coupling the planar surface of the electronic module to the cavity substrate, wherein said electronic module is recessed within said cavity.

42. The method of claim 41, further including the step of electrically attaching said electronic module to said substrate.

43. The method of claim 41, further including the step of electrically coupling and mechanically bonding an active integrated circuit chip to the planar surface of the electronic module, wherein said active integrated circuit chip is located within said opening and accessible for maintenance.

44. The method of claim 43, further including the step of thermally coupling a means for thermal management to said active integrated circuit chip, wherein said means for thermal management is located within said opening.

45. The method of claim 44, further including the step of sealing said means for thermal management to said substrate for protecting the electronic module from an external environment.

46. The method of claim 43, further in combination with a method for repairing the electronic package, including the step of removing said active integrated circuit chip from said electronic package.

47. A method for forming a computer unit comprising the steps of:

(a) providing a processor chip having a planar main surface, said processor chip including a cache memory controller;

(b) providing a first electronic module comprising a plurality of stacked integrated circuit (IC) chips and having a first planar surface, said first electronic module including a cache memory circuit; and

(c) mechanically and electrically coupling the first planar surface of the first electronic module to the planar surface of the processor chip such that the cache memory controller is electrically connected to the cache memory circuit.

48. The method of claim 47, wherein said providing step (b) includes providing the first electronic module with a second planar surface, said second planar surface having a first plurality of electrical contacts thereon, at least some electrical contacts of said first plurality of electrical contacts being electrically coupled to said processor chip for facilitating electrical contact to said processor chip.

49. The method of claim 48, wherein said computer unit includes a second processor chip having a planar main surface, and wherein said method includes mechanically and electrically coupling the planar main surface of the second processor chip to the second planar surface of the first electronic module.

50. The method of claim 48, wherein the providing step (b) further comprises providing a bussing chip within the plurality of stacked IC chips of the first electronic module, said bussing chip having a first edge surface parallel with the first planar surface of the first electronic module, and a second edge surface parallel with the second planar surface of the first electronic module, and wherein said bussing chip electrically connects the processor chip coupled to the first planar surface of the first electronic module to the at least some electrical contacts of the first plurality of electrical contacts coupled to the second planar surface of the electronic module.

51. The method of claim 48, wherein the computer unit includes an interposer substrate having a planar main surface, and wherein said method includes mechanically coupling the planar main surface of the interposer substrate to the second planar surface of the first electronic module such that said interposer substrate electrically attaches to the first plurality of electrical contacts and at least partially electrically interconnects the plurality of stacked IC chips of the first electronic module.

52. The method of claim 48, wherein said computer unit includes a second electronic module comprising a plurality of stacked IC chips and having a first planar surface, said second electronic module including a second memory circuit, and wherein said method further comprises mechanically coupling the first planar surface of the second electronic module to the second planar surface of the first electronic module such that the first electronic module and second electronic module are electrically coupled via the first plurality of electrical contacts such that the second electronic module is electrically coupled to the processor chip.

53. The computer unit of claim 52, wherein the second electronic module has a second planar surface, said second planar surface having a second plurality of electrical contacts thereon, and wherein said step of mechanically coupling the first planar surface of the second electronic module to the second planar surface of the first electronic module includes electrically coupling at least some of said electrical contacts of said second plurality of electrical contacts through said at least some electrical contacts of said first electronic module to said processor chip, for providing electrical contact to devices associated with said computer unit.

54. The computer unit of claim 53, wherein said computer unit includes a main memory controller chip having a planar main surface, and wherein said method includes mechanically coupling the planar main surface of the main memory controller chip to the second planar surface of the second electronic module such that said main memory controller chip is electrically coupled to the at least some electrical contacts of the second plurality of electrical contacts of the second electronic module.

55. The computer unit of claim 54, wherein the plurality of stacked IC chips of the second electronic module includes a bussing chip, said bussing chip having a first edge surface parallel with the first planar surface of the second electronic module, and a second edge surface parallel with the second planar surface of the second electronic module, and wherein said step of mechanically coupling the first planar surface of the second electronic module to the second planar surface of the first electronic module includes electrically connecting the at least some electrical contacts of the first plurality of electrical contacts of the first electronic module to the at least some electrical contacts of the second plurality of electrical contacts of the second electronic module using said bussing chip.

56. The computer unit of claim 47, wherein said providing step (b) includes providing a first electronic module having a main memory circuit, said electrical coupling step (c) being such that the main memory circuit functions in association with the processor chip.