Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers

• US 5,567,657 A
• Filed: 12/04/1995
• Issued: 10/22/1996
• Est. Priority Date: 12/04/1995
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Gorczyca, Thomas B., Wojnarowski, Robert J.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/567,386
• Time in Patent Office: 323 Days
• Field of Search: 437/209, 437/211, 437/212, 437/213, 437/214, 437/215, 437/216, 437/217, 437/218, 437/219, 437/220
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/76 Apparatus for connecting with build-up interconnects
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/4611 : by laminating two or more circuit boards H05K3/4652 takes precedence
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing

Abstract

First and second flexible interconnect structures are provided and each includes a flexible interconnect layer and a chip with a surface having chip pads attached to the flexible interconnect layer. Molding material is inserted between the flexible interconnect layers for encapsulating the respective chips. Vias in the flexible interconnect layers are formed to extend to selected chip pads, and a pattern of electrical conductors is applied which extends over the flexible interconnect layers and into the vias to couple selected ones of the chip pads.

Claims

1. A method for fabricating a two-sided molded circuit module with flexible interconnect layers, the method comprising the steps of:

providing first and second flexible interconnect structures, each flexible interconnect structure comprising a flexible interconnect layer having a chip surface and a chip with chip pads attached to the chip surface;

providing molding material between the chip surfaces of the flexible interconnect layers and thereby surrounding respective chips with the molding material;

solidifying the molding material;

forming vias in the flexible interconnect layers, at least some of the vias extending to selected chip pads;

applying a pattern of electrical conductors extending over the flexible interconnect layers and into the vias to couple selected ones of the chip pads.

2. The method of claim 1, wherein the step of forming vias further includes forming a via extending through one of the flexible interconnect structures and the molding material to the other of the flexible interconnect structures.

3. The method of claim 1, wherein each flexible interconnect layer comprises a plurality of polymer layers and at least one metallization layer.

4. The method of claim 1, wherein the molding material comprises an epoxy powder and the steps of providing and solidifying the molding material include applying heat under vacuum conditions.

5. The method of claim 1, further including forming a hole through the flexible interconnect structures and the molding material and coating the hole with an electrically conductive material.

6. The method of claim 1, further including positioning at least one electrically conductive pin between the first and second flexible interconnect structures and wherein the step of inserting molding material between the flexible interconnect layers for encapsulating the respective chips includes encapsulating the at least one pin and the step of forming vias extending to selected chip pads further includes forming a via to the at least one pin.

7. The method of claim 1, wherein the at least one chips are thin enough to withstand bending and further including the step of bending the module.

8. A method for fabricating a stack of two-sided molded circuit modules with flexible interconnect layers, the method comprising the steps of:

for each molded circuit module,

providing first and second flexible interconnect structures, each flexible interconnect structure comprising a flexible interconnect layer having a chip surface and a chip with chip pads attached to the chip surface,

providing molding material between the chip surfaces of the flexible interconnect layers and thereby surrounding respective chips with the molding material,

solidifying the molding material,

forming vias in the flexible interconnect layers, at least some of the vias extending to selected chip pads,

applying a pattern of electrical conductors extending over the flexible interconnect layers and into the vias to couple selected ones of the chip pads,

applying an epoxy mask over the pattern of electrical conductors, the mask having an opening over at least one of the vias, and

applying a soft conductive material in the at least one of the vias;

inserting a portion of a conductive ball in the soft conductive material of one of the molded circuit modules;

positioning the other of the molded circuit modules such that the soft conductive material of the other of the molded circuit modules at least partially surrounds a remaining portion of the conductive ball; and

hardening the epoxy masks and the soft conductive materials.