Formation of planarized insulating film by plasma-enhanced CVD of organic silicon compound

• US 5,567,661 A
• Filed: 06/03/1994
• Issued: 10/22/1996
• Est. Priority Date: 08/26/1993
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Hamada, Yumiko, Furuse, Takako, Uesugi, Hiroyuki, Nishio, Hidetoshi
• Primary Examiner(s): Kunemund, Robert
• Assistant Examiner(s): WHIPPLE, MATTHEW LAVERNE
• Application Number:
  US08/253,778
• Time in Patent Office: 872 Days
• Field of Search: 437/235, 437/238, 437/228
• US Class Current: 438/631
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02222 the compound being a silazane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3125 layers comprising silazane compounds

Abstract

A method of manufacturing a semiconductor device including the steps of: preparing a semiconductor substrate having convexities and concavities on the surface thereof; and generating plasma by using organic silicon having silazane bonding and oxidant and depositing a planarized insulating film on the semiconductor substrate by plasma chemical vapor deposition. The organic silicon may be HMCTSZ and the substrate temperature during deposition is preferably not higher than about 100° C., e.g. 50° C.

Claims

1. A method of manufacturing a semiconductor device having an insulating film comprising the steps of:

preparing a semiconductor substrate having one of convexities and concavities which create a step height on a surface thereof; and

generating plasma by using organic silicon having tri- or more silazane bonding and oxidant and depositing a planarized insulating film on said semiconductor substrate by plasma chemical vapor deposition at a substrate temperature of about 100°

C. or lower in order to significantly reduce the step height.

2. A method according to claim 1, wherein said organic silicon has a cyclosilazane bonding.

3. A method according to claim 1, wherein said organic silicon is (SiR₂ NR'"'"')₃, or (SiR₂ NR'"'"')₄ where each of R and R'"'"' is at least one of a phenyl, a vinyl, and C_n H_2n+1 (n=0, or positive integer).

4. A method according to claim 1, wherein said oxidant is at least one of O₂, N₂ O, and NO.

5. A method according to claim 1, wherein in said deposition step, plasma is generated by adding NH₃ or NF₃.

6. A method according to claim 1, wherein said step of preparing said semiconductor substrate further includes a step of forming a wiring pattern on the substrate.

7. A method according to claim 6, wherein said step of preparing said semiconductor substrate further includes a step of forming a conformable insulating film on the wiring pattern by CVD.

8. A method according to claim 1, further comprising a step of etching back said planarized insulating film at least above said one of convexities and concavities.

9. A method according to claim 6, further comprising the steps of:

forming a contact hole in said planarized insulating film and exposing said wiring pattern; and

selectively growing metal on said wiring pattern exposed in said contact hole.

10. A method according to claim 3, wherein said step of preparing said semiconductor substrate further includes a step of forming a conformable insulating film on the semiconductor substrate by CVD.

11. A method according to claim 8, wherein said step of preparing said semiconductor substrate further includes a step of forming a conformable insulating film on the semiconductor substrate by CVD.

12. A method according to claim 9, wherein said step of preparing said semiconductor substrate further includes a step of forming a conformable insulating film on the wiring pattern by CVD.

16. A method according to claim 2, wherein said organic silicon is (SiR₂ NR'"'"')₃, or (SiR₂ NR'"'"')₄ where R and R'"'"' are phenyl, vinyl or C_n H_2n+1 (n=0 or a positive integer).

17. A method according to claim 2, wherein said oxidant is at least one of O₂, N₂ O, and NO.

18. A method according to claim 2, wherein said step of generating plasma includes adding NH₃ or NF₃.

13. A method of depositing an insulating film comprising the steps of:

generating plasma by reacting a mixed gas containing oxygen atoms and an organic atom group represented by (SiR₂ NR'"'"')₃, or (SiR₂ NR'"'"')₄ where each of R and R'"'"' is C_n H_2n+1 (n=0, 1, 2, 3, . . . ), and depositing a planarized insulating film on a semiconductor substrate at a temperature of 100°

C. or lower using plasma chemical vapor deposition, said planarized insulating film significantly reducing a step height created by one of convexities and concavities on a surface of the semiconductor substrate.

14. A method according to claim 13, wherein said mixed gas is added with ammonia.

19. A method according to claim 13, wherein said atom group has a cyclosilazane bonding.

15. A method of depositing an insulating film comprising the step of:

generating plasma by reacting a mixed gas containing oxygen atoms and an organic atom group represented by (SiR₂ NR'"'"')₃, or (SiR₂ NR'"'"')₄ where each of R and R'"'"' is methyl, phenyl or H, and depositing a planarized insulating film on a semiconductor substrate at a temperature of 100°

C. or lower using plasma chemical vapor deposition, said planarized insulating film significantly reducing a step height created by one of convexities and concavities on a surface of the semiconductor substrate.

20. A method according to claim 15, wherein said atom group has a cyclosilazane bonding.