Probe apparatus having burn-in test function

• US 5,568,054 A
• Filed: 05/19/1995
• Issued: 10/22/1996
• Est. Priority Date: 07/31/1992
• Status: Expired due to Term

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited, Tokyo Electron Yamanashi Ltd. (Tokyo Electron Limited)
• Inventors: Iino, Shinji, Iida, Itaru
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): KHOSRAVI, KOURO
• Application Number:
  US08/444,888
• Time in Patent Office: 522 Days
• Field of Search: 324/755, 324/756, 324/760, 324/537, 324/754
• US Class Current: 324/750.05
• CPC Class Codes: G01R 31/2868 Complete testing stations; systems; procedures; software aspects

Abstract

A probe apparatus having a burn-in test function includes an apparatus body, a probe card, having a plurality of probes, for causing the plurality of probes to electrically contact a semiconductor wafer, a tester for measuring the electrical characteristics of the semiconductor wafer, heating and cooling mechanisms for applying a thermal stress to test target chips, as targets of the burn-in test, of the semiconductor wafer, and an electrical mechanism for applying an electrical stress to the chips.

Claims

1. A probe apparatus having a burn-in test function, comprising:

an apparatus body;

probe card means, having a plurality of probes, for causing said plurality of probes to directly electrically contact a plurality of electrode pads of at least one semiconductor chip included in a semiconductor wafer before cutting into semiconductor chips;

means for measuring electrical characteristics of the at least one semiconductor chip of the semiconductor wafer;

thermal stress means for applying a thermal stress to the wafer;

electrical stress means for applying an electrical stress to a test target chip through corresponding probes of said probe card means; and

measuring means for measuring an electrical parameter of the test target chip on the wafer to which a predetermined thermal and electrical stress is applied.

2. An apparatus according to claim 1, wherein said thermal stress means comprises a heating mechanism for heating the wafer.

3. An apparatus according to claim 2, wherein said thermal stress means further comprises a cooling mechanism for cooling the wafer.

4. An apparatus according to claim 3, further comprising wafer supporting means for supporting the wafer, and wherein said heating and cooling mechanisms are provided in said wafer supporting means.

5. An apparatus according to claim 1, wherein said electrical stress means comprises a voltage stress generating circuit and a pulse stress generating circuit.

6. An apparatus according to claim 1, wherein said electrical stress means comprises switching means for sequentially applying an electrical stress to a plurality of pads of the test target chip.

7. An apparatus according to claim 5, wherein said pulse stress generating circuit comprises a delay circuit for controlling a timing of a pulse to be applied to pads of the test target chip.

8. An apparatus according to claim 1, further comprising means for confirming contact between said plurality of probes and corresponding electrodes before the burn-in test.

9. An apparatus according to claim 1, wherein said thermal stress means and said electrical stress means apply a thermal stress and an electrical stress to a plurality of chips.

10. A probe apparatus having a burn-in test function, comprising:

an apparatus body;

probe card means, having a plurality of probes, for causing said plurality of probes to directly electrically contact a plurality of electrode pads of at least one semiconductor chip included in a semiconductor wafer before cutting into semiconductor chips;

means for measuring electrical characteristics of the at least one semiconductor chip of the semiconductor wafer;

thermal stress means for applying a thermal stress to the wafer;

electrical stress means for applying an electrical stress to a test target chip through corresponding probes of said probe card means;

power supply means for applying a power supply voltage to the test target chip;

measuring means for measuring an electrical parameter of the test target chip on the wafer to which a predetermined thermal and electrical stress is applied;

current monitor means for measuring a current flowing from said power supply means to the burn-in test target chip and outputting one of a current cutoff signal and a current decrease signal when a current measurement value exceeds a preset value; and

current control means for one of cutting off and decreasing the current flowing in the test target chip by the current cutoff signal sent from said current monitor means.

11. An apparatus according to claim 10, wherein said current monitor means comprises current measuring resistors respectively provided to power supply lines between the power supply means and a target chip and a common current measuring section for receiving a voltage across said current measuring resistors and measuring a current flowing in said current measuring resistors.

12. An apparatus according to claim 11, wherein said common current measuring section comprises a channel switching section for sequentially outputting the voltages across said current measuring resistors through channels, and measures a current sent from said channel switching section.

13. An apparatus according to claim 11, wherein said current monitor means comprises correcting means for correcting a current measurement value of said common current measuring section.

14. An apparatus according to claim 13, wherein said correcting means comprises a memory for storing correction values respectively corresponding to said channels, reads a correction value corresponding to a channel selected by said channel switching section from said memory, and corrects a current of said common current measuring section based on a readout correction value.

15. An apparatus according to claim 10, wherein said thermal stress means comprises a heating mechanism for heating the wafer.

16. An apparatus according to claim 15, wherein said thermal stress means further comprises a cooling mechanism for cooling the wafer.

17. An apparatus according to claim 16, further comprising wafer supporting means for supporting the wafer, and wherein said heating and cooling mechanisms are provided in said wafer supporting means.

18. An apparatus according to claim 10, wherein said electrical stress means comprises a voltage stress generating section and a pulse stress generating section.

19. An apparatus according to claim 10, wherein said electrical stress means comprises switching means for sequentially applying an electrical stress to the test target chip.

20. An apparatus according to claim 18, wherein said pulse stress generating section comprises a delay circuit for controlling a timing of a pulse to be applied to pads of the test target chip.

21. An apparatus according to claim 10, further comprising means for confirming contact between said plurality of probes and corresponding electrodes before the burn-in test.

22. An apparatus according to claim 10, wherein said thermal stress means and said electrical stress means apply a thermal stress and an electrical stress to a plurality of chips.