Memory architecture and devices, systems and methods utilizing the same
DCFirst Claim
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1. A memory device comprising:
- a plurality of arrays of memory cells;
a plurality of registers, each of said registers for exchanging parallel bits of data with a corresponding one of said arrays; and
data transfer circuitry for transferring parallel bits of data from any selected one of said arrays through the corresponding said register to any other selected one of said arrays through the corresponding said register.
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Abstract
A memory 200 is provided including a plurality of arrays 202 of memory cells 203. A plurality of registers 211 are also provided, each register 211 for exchanging parallel bits of data with a corresponding one of the arrays 202. Data transfer circuitry 210, 213 is included for transferring parallel bits of data from any selected one of the arrays 202 through the corresponding register 211 to any other selected one of the arrays 202 through the corresponding register 211.
12 Citations
20 Claims
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1. A memory device comprising:
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a plurality of arrays of memory cells; a plurality of registers, each of said registers for exchanging parallel bits of data with a corresponding one of said arrays; and data transfer circuitry for transferring parallel bits of data from any selected one of said arrays through the corresponding said register to any other selected one of said arrays through the corresponding said register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory subsystem comprising:
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a plurality of arrays of memory cells each arranged in rows and columns; for each said array, a row decoder and a column decoder for accessing selected ones of said cells of said array; for each said array, an associated register having a first parallel port coupled to said column decoder; a common bus coupled to a second parallel port of each said register; and circuitry for coupling data from accessed ones of said cells of a first selected one of said arrays to accessed ones of said cells of a second selected one of said arrays via said parallel ports of said associated registers and said bus. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method of transferring data in a memory including a plurality of arrays of memory cells, addressing circuitry for accessing selected ones of said cells of a selected array, a common bus, and a plurality of registers each for controlling the exchange of data between a corresponding array and the common bus, the method comprising the steps of:
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presenting at least one source address to the addressing circuitry to read data from selected cells of a selected source array; transferring the data from the source array to the common bus via the corresponding register; transferring the data to the register corresponding to a destination array; and presenting at least one destination address to the addressing circuitry to write data into selected cells of the destination array. - View Dependent Claims (18, 19, 20)
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Specification