Flash EEPROM system which maintains individual memory block cycle counts

• US 5,568,439 A
• Filed: 06/06/1995
• Issued: 10/22/1996
• Est. Priority Date: 06/08/1988
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Eliyahou Harari
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/468,061
• Time in Patent Office: 504 Days
• Field of Search: 365/182, 365/185, 365/218, 365/900, 365/185.01, 365/185.09, 365/185.18, 365/185.19, 365/185.22, 365/185.29, 365/185.33
• US Class Current: 365/185.09
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occurred. Individual records of the number of erase cycles experienced by blocks of flash EEPROM cells are kept, preferable as part of the blocks themselves, in order to maintain an endurance history of the cells within the blocks. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. A method of erasing an array of a plurality of electrically erasable and programmable read only memory (EEPROM) cells, the individual cells including a field effect transistor with a threshold voltage that is alterable by controlling a level of charge on a floating gate thereof and which has an erase electrode, said method comprising:

operating the memory array with the cells thereof being partitioned into individual distinct blocks of cells to be simultaneously erasable upon an erase voltage being applied to the erase electrodes thereof,

designating a plurality of cells within the individual blocks of cells for storing an indication of a number of erase cycles which the individual blocks have experienced,

reading, from the designated cells of a selected block to be erased, the experience number indicative of the number of erase cycles which the selected block has experienced,

temporarily storing outside of the selected block the experience number read from the selected block,

thereafter subjecting the selected block to an erase cycle by simultaneously applying an erase voltage to the erase electrodes of the memory cells therein,

verifying whether the cells within the selected block have been successfully erased,

terminating the erase cycle when the cells within the selected block have been successfully erased,

updating the experience number read from the selected block to reflect the occurrence of another erase cycle, and

after termination of the erase cycle, writing the updated experience number into said designated cells of the selected block.

2. The method according to claim 1, additionally comprising substituting another of said blocks to receive data designated for the selected block when the experience number stored in said selected memory block reaches a predetermined number.

3. The method according to claim 1, additionally comprising:

maintaining at least one of the memory blocks as a redundant memory block, and

replacing the selected block with the redundant block when the experience number stored in said selected memory block indicates that the selected block has been subjected to a predetermined number or erase cycles.

4. The method according to claim 1 which additionally comprises:

terminating the erase cycle, before the cells of the selected block have been successfully erased, when at least one other predetermined condition is detected to exist, and

thereafter substituting other cells for those cells of the selected block that are not successfully erased when the erase cycle is terminated.

5. The method according to claim 1 wherein the erase cycle includes:

pulsing the erase electrodes of the cells in said selected block for a predetermined time and voltage sufficient to alter the threshold voltages of their respective transistors but insufficient to completely erase the cells being pulsed,

thereafter determining the altered threshold voltages of the cells subjected to the pulsing, and

repeating a plurality of times said cycle of pulsing and reading.

6. The method according to claim 5 which additionally comprises:

terminating the erase cycle, before the cells of the selected block have been successfully erased, when the cycle of pulsing and reading has been repeated a preset maximum number of times, and

thereafter substituting other cells for those cells of the selected block that are not successfully erased when the erase cycle is terminated.

7. The method according to claim 5 wherein the cycle of pulsing and reading includes additionally pulsing cells in said selected block with a voltage that is increased an increment above that of the previous occurrence of pulsing and reading.

8. The method according to claim 7 which additionally comprises:

terminating the erase cycle, before the cells of the selected block have been successfully erased, when either the pulsing and reading has been repeated a preset maximum number of times or a predetermined maximum voltage for a pulse has been reached, and

thereafter substituting other cells for those cells of the selected block that are not successfully erased when the erase cycle is terminated.